SuccessChanges

Summary

  1. [XCore][docs] Fix XCore compiler writer documentation links. (details)
  2. [lldb][import-std-module] Add a test for typedef'd std types (details)
  3. [SLP][X86] Extend PR46983 tests to include SSE2,SSE42,AVX512BW test coverage (details)
  4. [clang][cli] Unify boolean marshalling (details)
  5. Add rsqrt lowering from standard to NVVM (details)
  6. [SVE] Fix crashes with inline assembly (details)
  7. [ARM] Remove dead instructions before creating VPT block bundles (details)
  8. [MLIR][SPIRV] Add initial support for OpSpecConstantOp. (details)
Commit 776bb71d88e48a77fc6788324d30bbc63581d6a9 by jryans
[XCore][docs] Fix XCore compiler writer documentation links.

Fix links to XMOS website. Add link for XS2 architecture.

Reviewed By: jryans

Differential Revision: https://reviews.llvm.org/D92019
The file was modifiedllvm/docs/CompilerWriterInfo.rst
Commit 6face9119c811e06cfb284755953ba6cdbdaa22b by Raphael Isemann
[lldb][import-std-module] Add a test for typedef'd std types
The file was modifiedlldb/test/API/commands/expression/import-std-module/vector/TestVectorFromStdModule.py
The file was modifiedlldb/test/API/commands/expression/import-std-module/vector/main.cpp
Commit 41d0666391131ddee451085c72ba6513872e7f6c by llvm-dev
[SLP][X86] Extend PR46983 tests to include SSE2,SSE42,AVX512BW test coverage

Noticed while reviewing D92824
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr46983.ll
Commit 083e035c47f6c73084ecf5ab7f41cddca19ce332 by jan_svoboda
[clang][cli] Unify boolean marshalling

Use lambdas with captures to replace the redundant infrastructure for marshalling of two boolean flags that control the same keypath.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D92773
The file was modifiedllvm/utils/TableGen/OptParserEmitter.cpp
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedllvm/include/llvm/Option/OptParser.td
Commit bb7d43e7d5f683fc3e7109072610dc8d176a3bf8 by frgossen
Add rsqrt lowering from standard to NVVM

Differential Revision: https://reviews.llvm.org/D92838
The file was modifiedmlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
The file was modifiedmlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
Commit 59f17b57d9c9abf86d8dcc05c49d3bbd807e29c7 by david.sherwood
[SVE] Fix crashes with inline assembly

All the crashes found compiling inline assembly are fixed in this
patch by changing AArch64TargetLowering::getRegForInlineAsmConstraint
to be more resilient to mismatched value and register types. For
example, it makes no sense to request a predicate register for
a nxv2i64 type and so on.

Tests have been added here:

  test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll

Differential Revision: https://reviews.llvm.org/D92554
The file was addedllvm/test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit 91fb9eac0b562cdfdc6b677f8ab2ee67f1ae1a77 by david.green
[ARM] Remove dead instructions before creating VPT block bundles

We remove VPNOT instructions in VPT blocks as we create them, turning
them into else predicates. We don't remove the dead instructions until
after the block has been created though. Because the VPNOT will have
killed the vpr register it used, this makes finalizeBundle add internal
flags to the vpr uses of any instructions after the VPNOT. These
incorrect flags can then confuse what is alive and what is not, leading
to machine verifier problems.

This patch removes them earlier instead, before the bundle is finalized
so that kill flags remain valid.

Differential Revision: https://reviews.llvm.org/D92227
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir
The file was modifiedllvm/lib/Target/ARM/MVEVPTBlockPass.cpp
Commit 6c69d3d68e9a4438b47422e49c0f2d69e2b8e1b7 by antiagainst
[MLIR][SPIRV] Add initial support for OpSpecConstantOp.

This commit adds initial support for SPIR-V OpSpecConstantOp
instruction. The following is introdcued:

- A new `spv.specConstantOperation` operation consisting of a single
region and of 2 operations within that regions (more details in the
docs of the op itself).
- A new `spv.yield` instruction that acts a terminator for
`spv.specConstantOperation`.

For now, the generic form of the new op is supported (i.e. no custom
parsing or printing). This will be done in a follow up patch.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D92232
The file was modifiedmlir/test/Dialect/SPIRV/structure-ops.mlir
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVOps.cpp
The file was modifiedmlir/include/mlir/Dialect/SPIRV/SPIRVStructureOps.td