SuccessChanges

Summary

  1. [gn build] Port ea6641085d0 (details)
  2. [NFC] Fix a gcc build break by using an explict constructor. (details)
  3. [Doc] Update branch name in Phabricator documentation (details)
  4. [RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions (details)
  5. [NPM] Support -fmerge-functions (details)
  6. [NFC] Fix a gcc build break by not using an initializer. (details)
  7. [RISCV][NFC] Fix Sext/Zext Tests (details)
  8. [AArch64] Don't try to compress jump tables if there are any inline asm instructions. (details)
Commit 57db6d20c6dadbc129f0bf842b2028e2716b67f6 by llvmgnsyncbot
[gn build] Port ea6641085d0
The file was modifiedllvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Core/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang/lib/Analysis/BUILD.gn
Commit 248b279cf04d9e439a1e426ffd24f2dfa93d02f8 by hoy
[NFC] Fix a gcc build break by using an explict constructor.
The file was modifiedllvm/lib/MC/MCParser/AsmParser.cpp
Commit 3631e080c4e85b762fffce63abfe3aadfa43884b by alexey.bader
[Doc] Update branch name in Phabricator documentation

master -> main

Differential Revision: https://reviews.llvm.org/D93020
The file was modifiedllvm/docs/Phabricator.rst
Commit 12406ade0625ffa3939e2fa684293e02eb8791ff by selliott
[RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions

There is an in-progress proposal for the following pseudo-instructions
in the assembler, to complement the existing `sext.w` rv64i instruction:
- sext.b
- sext.h
- zext.b
- zext.h
- zext.w

The `.b` and `.h` variants are available with rv32i and rv64i, and `zext.w` is
only available with `rv64i`.

These are implemented primarily as pseudo-instructions, as these instructions
expand to multiple real instructions. In the case of `zext.b`, this expands to a
single rv32/64i instruction, so it is implemented with an InstAlias (like
`sext.w` is on rv64i).

The proposal is available here: https://github.com/riscv/riscv-asm-manual/pull/61

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D92793
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
The file was modifiedllvm/test/MC/RISCV/rv32i-aliases-valid.s
The file was modifiedllvm/test/MC/RISCV/rv64i-aliases-valid.s
The file was modifiedllvm/test/CodeGen/RISCV/atomic-rmw.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoB.td
The file was modifiedllvm/test/CodeGen/RISCV/rv64Zbbp.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.td
The file was modifiedllvm/test/MC/RISCV/rv32i-aliases-invalid.s
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/alu8.ll
The file was modifiedllvm/test/CodeGen/RISCV/sext-zext-trunc.ll
The file was modifiedllvm/lib/Target/RISCV/RISCV.td
The file was modifiedllvm/test/CodeGen/RISCV/rv32Zbbp.ll
Commit ff7e1da68f2a74797d0d3454f6cac62064f7d982 by aeubanks
[NPM] Support -fmerge-functions

I tried to put it in the same place in the pipeline as the legacy PM.

Fixes PR48399.

Reviewed By: asbirlea, nikic

Differential Revision: https://reviews.llvm.org/D93002
The file was modifiedclang/test/CodeGenCXX/merge-functions.cpp
The file was modifiedclang/lib/CodeGen/BackendUtil.cpp
The file was modifiedllvm/include/llvm/Passes/PassBuilder.h
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
Commit 1dc0a8521f616af5897327e4c03098f9312e9c59 by hoy
[NFC] Fix a gcc build break by not using an initializer.

Test Plan:

Reviewers:

Subscribers:

Tasks:

Tags:
The file was modifiedllvm/lib/CodeGen/AsmPrinter/PseudoProbePrinter.cpp
Commit b7901e4c1a2ef0de73f133d5ecc6abbc3f427bdc by selliott
[RISCV][NFC] Fix Sext/Zext Tests

These were missed in a rebase of https://reviews.llvm.org/D92793
The file was modifiedllvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll
Commit c29af37c6c9d74ca330bd7f1d084f1f676ba2824 by Amara Emerson
[AArch64] Don't try to compress jump tables if there are any inline asm instructions.

Inline asm can contain constructs like .bytes which may have arbitrary size.
In some cases, this causes us to miscalculate the size of blocks and therefore
offsets, causing us to incorrectly compress a JT.

To be safe, just bail out of the whole thing if we find any inline asm.

Fixes PR48255

Differential Revision: https://reviews.llvm.org/D92865
The file was modifiedllvm/test/CodeGen/AArch64/jump-table-compress.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp
The file was modifiedllvm/test/CodeGen/AArch64/jump-table.ll