SuccessChanges

Summary

  1. [MLIR][SPIRV] Add support for GLSL F/U/SClamp. (details)
  2. Don't emit on op diagnostic in reproducer emission (details)
  3. [X86][SSE] combineReductionToHorizontal - add vXi8 ISD::MUL reduction handling (PR39709) (details)
Commit 076f87a86741f96c076cea9f9f2af17de55122a3 by antiagainst
[MLIR][SPIRV] Add support for GLSL F/U/SClamp.

Adds support for 3 ternary ops from SPIR-V extended instructions for
GLSL. Namely, adds support for FClamp, UClamp, and SClamp.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D92859
The file was modifiedmlir/test/Dialect/SPIRV/glslops.mlir
The file was modifiedmlir/include/mlir/Dialect/SPIRV/SPIRVBase.td
The file was modifiedmlir/test/Dialect/SPIRV/Serialization/glsl-ops.mlir
The file was modifiedmlir/include/mlir/Dialect/SPIRV/SPIRVGLSLOps.td
Commit 9c3fa3d84d5cdcdcdb5b6961f2c587f84e7caa39 by jpienaar
Don't emit on op diagnostic in reproducer emission

This avoids dumping the module post emitting a reproducer, which results in
many MB logs where a reproducer has already been neatly generated.

Differential Revision: https://reviews.llvm.org/D93165
The file was modifiedmlir/lib/Pass/Pass.cpp
Commit 47321c311bdbe0145b9bf45d822185c37b19fa50 by llvm-dev
[X86][SSE] combineReductionToHorizontal - add vXi8 ISD::MUL reduction handling (PR39709)

Default expansion leads to repeated extensions/truncations to/from vXi16 which shuffle combining and demanded elts can't completely unravel.

Better just to promote (any_extend) the input and perform a vXi16 reduction.

We'll be able to remove a lot of this if we ever get decent legalization support for reduction intrinsics in SelectionDAG.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-mul.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.h