SuccessChanges

Summary

  1. [XRay] Remove unnecessary <x86intrin.h> include (details)
  2. [AMDGPU][NFC] Remove unused VOP3Mods0Clamp (details)
  3. [AMDGPU][NFC] Rename opsel/opsel_hi/neg_lo/neg_hi with suffix 0 (details)
  4. [ARM] Improve handling of empty VPT blocks in tail predicated loops (details)
  5. [SVE][CodeGen] Lower scalable floating-point vector reductions (details)
  6. [IRCE] Add test case for PR48051 (details)
Commit 55f07a340070ebfb53eef68a624956d11936b1fe by raul
[XRay] Remove unnecessary <x86intrin.h> include

It hasn't been necessary since commit 4d4ed0e288bf1f3a90fba6e5b56bc25e2fe961c3 (D43278).

Reviewed By: dberris

Differential Revision: https://reviews.llvm.org/D93196
The file was modifiedcompiler-rt/lib/xray/xray_x86_64.inc
Commit af4570cd3ab94dd52574874b0e9c91a4f6e39272 by carl.ritson
[AMDGPU][NFC] Remove unused VOP3Mods0Clamp

This is unused and the selection function does not exist.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D93188
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
Commit 62c246eda24c362f1aa5a71f2cf11f9df5642460 by carl.ritson
[AMDGPU][NFC] Rename opsel/opsel_hi/neg_lo/neg_hi with suffix 0

These parameters set a default value of 0, so I believe they
should include a 0 suffix. This allows for versions which do not
set a default value in future.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D93187
The file was modifiedllvm/lib/Target/AMDGPU/VOP3PInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
Commit 1de3e7fd620bc9db2df96a12401bde4bde722785 by david.green
[ARM] Improve handling of empty VPT blocks in tail predicated loops

A vpt block that just contains either VPST;VCTP or VPT;VCTP, once the
VCTP is removed will become invalid. This fixed the first by removing
the now empty block and bails out for the second, as we have no simple
way of converting a VPT to a VCMP.

Differential Revision: https://reviews.llvm.org/D92369
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir
Commit c5ced82c8e49ad629d9c62157655eb31a39c0fad by kerry.mclaughlin
[SVE][CodeGen] Lower scalable floating-point vector reductions

Changes in this patch:
-  Minor changes to the LowerVECREDUCE_SEQ_FADD function added by @cameron.mcinally
   to also work for scalable types
- Added TableGen patterns for FP reductions with unpacked types (nxv2f16, nxv4f16 & nxv2f32)
- Asserts added to expandFMINNUM_FMAXNUM & expandVecReduceSeq for scalable types

Reviewed By: cameron.mcinally

Differential Revision: https://reviews.llvm.org/D93050
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was addedllvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll
The file was addedllvm/test/CodeGen/AArch64/sve-fp-reduce.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit 5a02bf4f950e530c3819bf4c54c4382453a82cec by llvm-dev
[IRCE] Add test case for PR48051
The file was addedllvm/test/Transforms/IRCE/pr48051.ll