SuccessChanges

Summary

  1. [LV] Add reduction test, which exposed a crash in a pending patch. (details)
  2. [X86][AVX] LowerBUILD_VECTOR - reduce 256/512-bit build vectors with zero/undef upper elements + pad. (details)
  3. [X86] Remove trailing whitespace. NFC. (details)
Commit 8a7e770638f00c5c8657044b44ca34f471d29511 by flo
[LV] Add reduction test, which exposed a crash in a pending patch.
The file was addedllvm/test/Transforms/LoopVectorize/select-reduction.ll
Commit 15a31389b2ead8fa7052a4378b76b5d686d29ad7 by llvm-dev
[X86][AVX] LowerBUILD_VECTOR - reduce 256/512-bit build vectors with zero/undef upper elements + pad.

As discussed on D92645, we don't do a good job of recognising when we don't require the full width of a ymm/zmm build vector because the upper elements are undef/zero.

This commit allows us to make use of implicit zeroing of upper elements with AVX instructions, which we emulate in DAG with a INSERT_SUBVECTOR into the bottom of a undef/zero vector of the original type.

This exposed a limitation in getTargetConstantBitsFromNode which didn't extract bits from INSERT_SUBVECTORs of different element widths which I've included as well to prevent a couple of regressions.
The file was modifiedllvm/test/CodeGen/X86/pr46532.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
The file was modifiedllvm/test/CodeGen/X86/pr29112.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
The file was modifiedllvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
The file was modifiedllvm/test/CodeGen/X86/trunc-subvector.ll
Commit bd0709266911bce2f1e8a875f9ed49d56953f323 by llvm-dev
[X86] Remove trailing whitespace. NFC.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp

Summary

  1. Use clang-stage2-Rthinlto host-compilers to for LLDB jobs (details)
Commit 44410c491239c1e143712180c16e8fda6d5c307e by Raphael Isemann
Use clang-stage2-Rthinlto host-compilers to for LLDB jobs

This should prevent that we have no regression information from LLDB because
the latest stage1 Clang we use as the host-compiler can't compile LLVM itself.
The file was modifiedzorg/jenkins/jobs/jobs/lldb-cmake
The file was modifiedzorg/jenkins/jobs/jobs/lldb-cmake-sanitized
The file was modifiedzorg/jenkins/jobs/jobs/lldb-cmake-reproducers
The file was modifiedzorg/jenkins/jobs/jobs/lldb-cmake-matrix
The file was modifiedzorg/jenkins/jobs/jobs/lldb-cmake-standalone