SuccessChanges

Summary

  1. AMDGPU: Remove SGPRSpillVGPRDefinedSet hack (details)
  2. [RISCV] V does not imply F. (details)
  3. [RISCV] Define vector mul/div/rem intrinsics. (details)
  4. [RISCV] Define vector widening mul intrinsics. (details)
Commit f333736757e9df318b2c3490c61341966024561b by Matthew.Arsenault
AMDGPU: Remove SGPRSpillVGPRDefinedSet hack

These VGPRs should be reserved and therefore do not need "correct"
liveness. They should not have undef uses, which can still cause
issues.
The file was modifiedllvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/spill192.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/vgpr-spill.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir
The file was modifiedllvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
Commit f03609b5c7531061be659e36824d37ef86a1fdf4 by kai.wang
[RISCV] V does not imply F.

If users want to use vector floating point instructions, they need to
specify 'F' extension additionally.

Differential Revision: https://reviews.llvm.org/D93282
The file was modifiedllvm/test/MC/RISCV/rvv/fmul.s
The file was modifiedllvm/lib/Target/RISCV/RISCV.td
The file was modifiedllvm/test/MC/RISCV/rvv/fothers.s
The file was modifiedllvm/test/MC/RISCV/rvv/fsub.s
The file was modifiedllvm/test/MC/RISCV/rvv/fmv.s
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vle-rv32.ll
The file was modifiedllvm/test/MC/RISCV/rvv/fcompare.s
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vse-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vse-rv64.ll
The file was modifiedllvm/test/MC/RISCV/rvv/sign-injection.s
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoV.td
The file was modifiedllvm/test/MC/RISCV/rvv/fadd.s
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vle-rv64.ll
The file was modifiedllvm/test/MC/RISCV/rvv/convert.s
The file was modifiedllvm/test/MC/RISCV/rvv/fminmax.s
The file was modifiedllvm/test/MC/RISCV/rvv/fmacc.s
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/MC/RISCV/rvv/freduction.s
The file was modifiedllvm/test/MC/RISCV/rvv/fdiv.s
Commit dd5281e7cce55d64cb0efd272172c1b4f8bf5bb0 by kai.wang
[RISCV] Define vector mul/div/rem intrinsics.

Define vector mul/div/rem intrinsics and lower them to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

Differential Revision: https://reviews.llvm.org/D93380
The file was addedllvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsRISCV.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
Commit a5e4a513b0410c7ebafc7b8cc00903220536f555 by kai.wang
[RISCV] Define vector widening mul intrinsics.

Define vector widening mul intrinsics and lower them to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

Differential Revision: https://reviews.llvm.org/D93381
The file was addedllvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsRISCV.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll