SuccessChanges

Summary

  1. [LV] Disable epilogue vectorization for scalable VFs (details)
  2. [lldb] [unittests] Add tests for NetBSD register offsets/sizes (details)
  3. [lldb] [unittests] Filter FreeBSD through CMake rather than #ifdef (details)
  4. [mlir] Fix syntax error in markdown documentation (details)
  5. [lldb-vscode] Speculative fix for raciness in TestVSCode_attach (details)
  6. [libc] revamp memory function benchmark (details)
  7. [IRBuilder] Generalize debug loc handling for arbitrary metadata. (details)
  8. [NFC][AArch64] Move AArch64 MSR/MRS into a new decoder namespace (details)
  9. [NFC][AArch64] Capturing multiple feature requirements in AsmParser messages (details)
  10. [ARM][AArch64] Adding basic support for the v8.7-A architecture (details)
  11. [AArch64] Add a GPR64x8 register class (details)
  12. [AArch64] Adding the v8.7-A LD64B/ST64B Accelerator extension (details)
  13. [ARM][AAarch64] Initial command-line support for v8.7-A (details)
  14. [ARM] Adding v8.7-A command-line support for the ARM target (details)
  15. [lld-macho] Add support for weak references (details)
  16. [lld-macho] Use LC_LOAD_WEAK_DYLIB for dylibs with only weakrefs (details)
  17. [InstCombine] Remove scalable vector restriction in InstCombineCasts (details)
  18. [SimplifyCFG] Preserve !annotation in FoldBranchToCommonDest. (details)
  19. [clang-tidy][NFC] Reduce copies of Intrusive..FileSystem (details)
Commit 1fd3a04775971d12e1063ceb2b22647fd4643acc by cullen.rhodes
[LV] Disable epilogue vectorization for scalable VFs

Epilogue vectorization doesn't support scalable vectorization factors
yet, disable it for now.

Reviewed By: sdesmalen, bmahjour

Differential Revision: https://reviews.llvm.org/D93063
The file was modifiedllvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-limitations.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 56440359d093ea6f8e9c91064fdd47928cf07092 by mgorny
[lldb] [unittests] Add tests for NetBSD register offsets/sizes

Differential Revision: https://reviews.llvm.org/D93299
The file was addedlldb/unittests/Process/Utility/RegisterContextNetBSDTest_x86_64.cpp
The file was addedlldb/unittests/Process/Utility/RegisterContextNetBSDTest_i386.cpp
The file was modifiedlldb/unittests/Process/Utility/CMakeLists.txt
Commit 37f99a56065209627020428cecb78f55dfa90580 by mgorny
[lldb] [unittests] Filter FreeBSD through CMake rather than #ifdef
The file was modifiedlldb/unittests/Process/Utility/RegisterContextFreeBSDTest.cpp
The file was modifiedlldb/unittests/Process/Utility/CMakeLists.txt
Commit eb4917d121e21aaf8406efe3d5e4f1f06cb7c238 by zinenko
[mlir] Fix syntax error in markdown documentation
The file was modifiedmlir/docs/Dialects/LLVM.md
Commit e7a3c4c11e84ba99c3682ae6cf20c398f16cf3f5 by pavel
[lldb-vscode] Speculative fix for raciness in TestVSCode_attach

The test appears to expect the inferior to be stopped, but the custom
"attach commands" leave it in a running state.

It's unclear how this could have ever worked.
The file was modifiedlldb/test/API/tools/lldb-vscode/attach/TestVSCode_attach.py
Commit deae7e982a3b08996455e2cdfdc5062bf37895a3 by gchatelet
[libc] revamp memory function benchmark

The benchmarking infrastructure can now run in two modes:
- Sweep Mode: which generates a ramp of size values (same as before),
- Distribution Mode: allows the user to select a distribution for the size paramater that is representative from production.

The analysis tool has also been updated to handle both modes.

Differential Revision: https://reviews.llvm.org/D93210
The file was removedlibc/benchmarks/Memcmp.cpp
The file was modifiedlibc/benchmarks/LibcMemoryBenchmark.cpp
The file was modifiedlibc/benchmarks/README.md
The file was modifiedlibc/benchmarks/LibcBenchmark.h
The file was removedlibc/benchmarks/LibcMemoryBenchmarkMain.h
The file was modifiedlibc/benchmarks/JSON.h
The file was addedlibc/benchmarks/libc-benchmark-analysis.py3
The file was removedlibc/benchmarks/Memcpy.cpp
The file was modifiedlibc/benchmarks/CMakeLists.txt
The file was modifiedlibc/benchmarks/JSON.cpp
The file was removedlibc/benchmarks/configuration_small.json
The file was modifiedlibc/benchmarks/JSONTest.cpp
The file was removedlibc/benchmarks/configuration_big.json
The file was modifiedlibc/benchmarks/LibcMemoryBenchmark.h
The file was modifiedlibc/benchmarks/LibcMemoryBenchmarkTest.cpp
The file was modifiedlibc/benchmarks/MemorySizeDistributions.cpp
The file was removedlibc/benchmarks/Memset.cpp
The file was modifiedlibc/benchmarks/RATIONALE.md
The file was removedlibc/benchmarks/render.py3
The file was modifiedlibc/benchmarks/LibcMemoryBenchmarkMain.cpp
Commit 29077ae860bcf3c9e9f2ce67ca7dfe691b6fa148 by flo
[IRBuilder] Generalize debug loc handling for arbitrary metadata.

This patch extends IRBuilder to allow adding/preserving arbitrary
metadata on created instructions.

Instead of using references to specific metadata nodes (like DebugLoc),
IRbuilder now keeps a vector of (metadata kind, MDNode *) pairs, which
are added to each created instruction.

The patch itself is a NFC and only moves the existing debug location
handling over to the new system. In a follow-up patch it will be used to
preserve !annotation metadata besides !dbg.

The current approach requires iterating over MetadataToCopy to avoid
adding duplicates, but given that the number of metadata kinds to
copy/preserve is going to be very small initially (0, 1 (for !dbg) or 2
(!dbg and !annotation)) that should not matter.

Reviewed By: lebedev.ri

Differential Revision: https://reviews.llvm.org/D93400
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp
The file was modifiedllvm/include/llvm/IR/IRBuilder.h
The file was modifiedllvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
Commit b5bbb4b2b75302d1d8080529ec7e9737a507ff1d by lucas.prates
[NFC][AArch64] Move AArch64 MSR/MRS into a new decoder namespace

This removes the general forms of the AArch64 MSR and MRS instructions
from the same decoding table that contains many more specific
instructions that supersede them. They're now in a separate decoding
table of their own, called "Fallback", which is only consulted in the
event of the main decoder table failing to produce an answer.

This should avoid decoding conflicts on future specialized instructions
in the MSR space.

Patch written by Simon Tatham.

Reviewed By: ostannard

Differential Revision: https://reviews.llvm.org/D91771
The file was modifiedllvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
Commit 83ea17fc5f742abb0ab0757ef9e667a4e2b39ea8 by lucas.prates
[NFC][AArch64] Capturing multiple feature requirements in AsmParser messages

This enables the capturing of multiple required features in the AArch64
AsmParser's SysAlias error messages.

Reviewed By: ostannard

Differential Revision: https://reviews.llvm.org/D92388
The file was modifiedllvm/test/MC/AArch64/armv8.5a-mte.s
The file was modifiedllvm/test/MC/AArch64/armv8.5a-persistent-memory.s
The file was modifiedllvm/test/MC/AArch64/armv8.5a-predres.s
The file was modifiedllvm/test/MC/AArch64/armv8.4a-tlb.s
The file was modifiedllvm/test/MC/AArch64/directive-arch_extension-negative.s
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
The file was modifiedllvm/test/MC/AArch64/armv8.2a-at.s
The file was modifiedllvm/test/MC/AArch64/armv8.2a-persistent-memory.s
Commit 42b92b31b8b8ee9fdcd68adfe57db11561a5edcd by lucas.prates
[ARM][AArch64] Adding basic support for the v8.7-A architecture

This introduces support for the v8.7-A architecture through a new
subtarget feature called "v8.7a". It adds two new "WFET" and "WFIT"
instructions, the nXS limited-TLB-maintenance qualifier for DSB and TLBI
instructions, a new CPU id register, ID_AA64ISAR2_EL1, and the new
HCRX_EL2 system register.

Based on patches written by Simon Tatham and Victor Campos.

Reviewed By: ostannard

Differential Revision: https://reviews.llvm.org/D91772
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was addedllvm/test/MC/AArch64/armv8.7a-wfxt.s
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/lib/Target/ARM/ARMSubtarget.h
The file was addedllvm/test/MC/AArch64/armv8.7a-xs.s
The file was addedllvm/test/MC/AArch64/armv8.7a-hcx.s
The file was modifiedllvm/test/MC/AArch64/basic-a64-diagnostics.s
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
The file was modifiedllvm/test/MC/AArch64/arm64-system-encoding.s
The file was addedllvm/test/MC/Disassembler/AArch64/armv8.7a-hcx.txt
The file was modifiedllvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64Subtarget.h
The file was modifiedllvm/lib/Target/AArch64/AArch64SystemOperands.td
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64.td
The file was addedllvm/test/MC/Disassembler/AArch64/armv8.7a-wfxt.txt
The file was modifiedllvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
The file was addedllvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
The file was modifiedllvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
Commit 97c006aabb6c831d68204bcb4aad8670af695618 by lucas.prates
[AArch64] Add a GPR64x8 register class

This adds a GPR64x8 register class that will be needed as the data
operand to the LD64B/ST64B family of instructions in the v8.7-A
Accelerator Extension, which load or store a contiguous range of eight
x-regs. It has to be its own register class so that register allocation
will have visibility of the full set of registers actually read/written
by the instructions, which will be needed when we add intrinsics and/or
inline asm access to this piece of architecture.

Patch written by Simon Tatham.

Reviewed By: ostannard

Differential Revision: https://reviews.llvm.org/D91774
The file was modifiedllvm/lib/Target/AArch64/AArch64RegisterInfo.td
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
The file was modifiedllvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
Commit 313889191ea14e978635b5cdf8838f3212d068a4 by lucas.prates
[AArch64] Adding the v8.7-A LD64B/ST64B Accelerator extension

This adds support for the v8.7-A LD64B/ST64B Accelerator extension
through a subtarget feature called "ls64". It adds four 64-byte
load/store instructions with an operand in the new GPR64x8 register
class, and one system register that's part of the same extension.

Based on patches written by Simon Tatham.

Reviewed By: ostannard

Differential Revision: https://reviews.llvm.org/D91775
The file was addedllvm/test/MC/Disassembler/AArch64/armv8.7a-ls64.txt
The file was modifiedllvm/lib/Target/AArch64/AArch64.td
The file was modifiedllvm/lib/Target/AArch64/AArch64SystemOperands.td
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
The file was addedllvm/test/MC/AArch64/armv8.7a-ls64.s
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64Subtarget.h
Commit c4d851b079037e9b7dd3f8613dd1c8a4f3db99fa by lucas.prates
[ARM][AAarch64] Initial command-line support for v8.7-A

This introduces command-line support for the 'armv8.7-a' architecture name
(and an alias without the '-', as usual), and for the 'ls64' extension name.

Based on patches written by Simon Tatham.

Reviewed By: ostannard

Differential Revision: https://reviews.llvm.org/D91776
The file was modifiedllvm/lib/Support/ARMTargetParser.cpp
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
The file was modifiedclang/lib/Driver/ToolChains/Arch/AArch64.cpp
The file was addedclang/test/Driver/aarch64-ls64.c
The file was modifiedllvm/include/llvm/Support/AArch64TargetParser.h
The file was modifiedllvm/unittests/Support/TargetParserTest.cpp
The file was modifiedllvm/lib/Support/AArch64TargetParser.cpp
The file was modifiedclang/lib/Basic/Targets/AArch64.h
The file was modifiedclang/test/Driver/aarch64-cpus.c
The file was modifiedllvm/include/llvm/Support/AArch64TargetParser.def
The file was modifiedclang/lib/Basic/Targets/AArch64.cpp
Commit c5046ebdf6e4be9300677c538ecaa61648c31248 by lucas.prates
[ARM] Adding v8.7-A command-line support for the ARM target

This extends the command-line support for the 'armv8.7-a' architecture
name to the ARM target.

Based on a patch written by Momchil Velikov.

Reviewed By: ostannard

Differential Revision: https://reviews.llvm.org/D93231
The file was modifiedclang/lib/Basic/Targets/ARM.cpp
The file was modifiedclang/test/Driver/arm-cortex-cpus.c
The file was modifiedllvm/lib/Support/ARMTargetParser.cpp
The file was modifiedllvm/include/llvm/Support/ARMTargetParser.def
The file was modifiedllvm/unittests/Support/TargetParserTest.cpp
The file was modifiedllvm/lib/Target/ARM/ARMPredicates.td
The file was modifiedclang/test/Preprocessor/arm-target-features.c
The file was modifiedllvm/include/llvm/ADT/Triple.h
The file was modifiedllvm/lib/Target/ARM/ARM.td
The file was modifiedllvm/lib/Support/Triple.cpp
Commit 811444d7a173e696f975f8d41626f6809439f726 by jezng
[lld-macho] Add support for weak references

Weak references need not necessarily be satisfied at runtime (but they must
still be satisfied at link time). So symbol resolution still works as per usual,
but we now pass around a flag -- ultimately emitting it in the bind table -- to
indicate if a given dylib symbol is a weak reference.

ld64's behavior for symbols that have both weak and strong references is
a bit bizarre. For non-function symbols, it will emit a weak import. For
function symbols (those referenced by BRANCH relocs), it will emit a
regular import. I'm not sure what value there is in that behavior, and
since emulating it will make our implementation more complex, I've
decided to treat regular weakrefs like function symbol ones for now.

Fixes PR48511.

Reviewed By: #lld-macho, thakis

Differential Revision: https://reviews.llvm.org/D93369
The file was modifiedlld/MachO/Symbols.h
The file was modifiedlld/MachO/SymbolTable.h
The file was modifiedlld/MachO/Driver.cpp
The file was addedlld/test/MachO/weak-reference.s
The file was modifiedlld/MachO/SymbolTable.cpp
The file was modifiedlld/test/MachO/symtab.s
The file was modifiedlld/MachO/InputFiles.cpp
The file was modifiedlld/MachO/SyntheticSections.cpp
Commit 4c8276cdc120c24410dcd62a9986f04e7327fc2f by jezng
[lld-macho] Use LC_LOAD_WEAK_DYLIB for dylibs with only weakrefs

Note that dylibs without *any* refs will still be loaded in the usual
(strong) fashion.

Reviewed By: #lld-macho, thakis

Differential Revision: https://reviews.llvm.org/D93435
The file was modifiedlld/test/MachO/weak-import.s
The file was modifiedlld/MachO/Writer.cpp
The file was modifiedlld/MachO/Symbols.h
The file was modifiedlld/MachO/InputFiles.cpp
The file was modifiedlld/MachO/InputFiles.h
Commit 01383999037760288f617e24084991eaf6bd9272 by JunMa
[InstCombine] Remove scalable vector restriction in InstCombineCasts

Differential Revision: https://reviews.llvm.org/D93389
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
The file was modifiedllvm/test/Transforms/InstCombine/addrspacecast.ll
The file was modifiedllvm/test/Transforms/InstCombine/trunc-extractelement.ll
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedllvm/test/Transforms/InstCombine/ptr-int-cast.ll
The file was modifiedllvm/test/Transforms/InstCombine/vec_shuffle.ll
Commit 75c04bfc61d6cc5623eadd8a04f86c315dacd823 by flo
[SimplifyCFG] Preserve !annotation in FoldBranchToCommonDest.

When folding a branch to a common destination, preserve !annotation on
the created instruction, if the terminator of the BB that is going to be
removed has !annotation. This should ensure that !annotation is attached
to the instructions that 'replace' the original terminator.

Reviewed By: jdoerfert, lebedev.ri

Differential Revision: https://reviews.llvm.org/D93410
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
The file was modifiedllvm/test/Transforms/SimplifyCFG/annotations.ll
Commit 64badecd447f2358812a2e747b2683d34071f5a5 by n.james93
[clang-tidy][NFC] Reduce copies of Intrusive..FileSystem

Swapped a few instances where a move is more optimal or the target doesn't need to hold a reference.
The file was modifiedclang-tools-extra/clang-tidy/ClangTidy.cpp
The file was modifiedclang-tools-extra/clang-tidy/tool/ClangTidyMain.cpp