SuccessChanges

Summary

  1. [DAGCombiner] Improve shift by select of constant (details)
  2. [RISCV] Define vsadd/vsaddu/vssub/vssubu intrinsics. (details)
Commit 385e9a2a047bc0bee13a21a9016763e694a686a3 by qshanz
[DAGCombiner] Improve shift by select of constant

Clean up a TODO, to support folding a shift of a constant by a
select of constants, on targets with different shift operand sizes.

Reviewed By: RKSimon, lebedev.ri

Differential Revision: https://reviews.llvm.org/D90349
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/X86/dagcombine-select.ll
The file was modifiedllvm/test/CodeGen/PowerPC/select_const.ll
The file was modifiedllvm/test/CodeGen/AArch64/select_const.ll
Commit ee2cb90e3bbe5cc6d027b1f821458eb267da516f by kai.wang
[RISCV] Define vsadd/vsaddu/vssub/vssubu intrinsics.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>
Co-Authored-by: Monk Chiang <monk.chiang@sifive.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D93366
The file was addedllvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsRISCV.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll