Commit
4652718ee38c519c6bb9470758d07430b0de02dd
by lxfindCleanup coro-inline.ll
Following up with the comments in D92706. - Use -passes instead of -enable-new-pm - CoroEarly should happen before AlwaysInliner, adjust it. - Remove some unnecessary barriers (still kept one) - Cleanup unnecessary debug info
Differential Revision: https://reviews.llvm.org/D93342
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 | llvm/test/Transforms/Coroutines/coro-inline.ll |
Commit
e1c1adf9dc1a6e535ff6a8d5373e968f772e68e1
by david.green[ARM] Match dual lane vmovs from insert_vector_elt
MVE has a dual lane vector move instruction, capable of moving two general purpose registers into lanes of a vector register. They look like one of: vmov q0[2], q0[0], r2, r0 vmov q0[3], q0[1], r3, r1 They only accept these lane indices though (and only insert into an i32), either moving lanes 1 and 3, or 0 and 2.
This patch adds some tablegen patterns for them, selecting from vector inserts elements. Because the insert_elements are know to be canonicalized to ascending order there are several patterns that we need to select. These lane indices are:
3 2 1 0 -> vmovqrr 31; vmovqrr 20 3 2 1 -> vmovqrr 31; vmov 2 3 1 -> vmovqrr 31 2 1 0 -> vmovqrr 20; vmov 1 2 0 -> vmovqrr 20
With the top one being the most common. All other potential patterns of lane indices will be matched by a combination of these and the individual vmov pattern already present. This does mean that we are selecting several machine instructions at once due to the need to re-arrange the inserts, but in this case there is nothing else that will attempt to match an insert_vector_elt node.
This is a recommit of 6cc3d80a84884a79967fffa4596c14001b8ba8a3 after fixing the backward instruction definitions.
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 | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp |
 | llvm/test/CodeGen/Thumb2/mve-vld4-post.ll |
 | llvm/test/CodeGen/Thumb2/mve-phireg.ll |
 | llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll |
 | llvm/test/CodeGen/Thumb2/mve-vmull-loop.ll |
 | llvm/test/CodeGen/Thumb2/mve-neg.ll |
 | llvm/test/CodeGen/Thumb2/mve-vld2-post.ll |
 | llvm/test/CodeGen/Thumb2/mve-vst4.ll |
 | llvm/test/CodeGen/Thumb2/mve-shifts.ll |
 | llvm/test/CodeGen/Thumb2/mve-vld4.ll |
 | llvm/test/CodeGen/Thumb2/mve-div-expand.ll |
 | llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll |
 | llvm/test/CodeGen/Thumb2/mve-vld3.ll |
 | llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll |
 | llvm/test/CodeGen/Thumb2/mve-minmax.ll |
 | llvm/test/CodeGen/Thumb2/mve-vqshrn.ll |
 | llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll |
 | llvm/test/CodeGen/Thumb2/mve-soft-float-abi.ll |
 | llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll |
 | llvm/test/CodeGen/Thumb2/mve-pred-ext.ll |
 | llvm/test/CodeGen/Thumb2/mve-pred-and.ll |
 | llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll |
 | llvm/test/CodeGen/Thumb2/mve-vqmovn.ll |
 | llvm/test/CodeGen/Thumb2/mve-abs.ll |
 | llvm/test/CodeGen/Thumb2/mve-vst2.ll |
 | llvm/test/CodeGen/Thumb2/mve-vcmpr.ll |
 | llvm/test/CodeGen/Thumb2/mve-pred-not.ll |
 | llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll |
 | llvm/test/CodeGen/Thumb2/mve-gather-ind8-unscaled.ll |
 | llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll |
 | llvm/test/CodeGen/Thumb2/mve-vdup.ll |
 | llvm/test/CodeGen/Thumb2/mve-widen-narrow.ll |
 | llvm/test/CodeGen/Thumb2/mve-vcvt.ll |
 | llvm/test/CodeGen/Thumb2/mve-vcmp.ll |
 | llvm/test/CodeGen/Thumb2/mve-scatter-ind8-unscaled.ll |
 | llvm/test/CodeGen/Thumb2/mve-sext.ll |
 | llvm/test/CodeGen/Thumb2/mve-pred-xor.ll |
 | llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll |
 | llvm/test/CodeGen/Thumb2/mve-vld2.ll |
 | llvm/lib/Target/ARM/ARMInstrMVE.td |
 | llvm/test/CodeGen/Thumb2/mve-simple-arith.ll |
 | llvm/test/CodeGen/Thumb2/mve-gather-increment.ll |
 | llvm/test/CodeGen/Thumb2/mve-vabdus.ll |
 | llvm/test/CodeGen/Thumb2/active_lane_mask.ll |
 | llvm/test/CodeGen/Thumb2/mve-gather-ind32-unscaled.ll |
 | llvm/test/CodeGen/Thumb2/mve-vcmpz.ll |
 | llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll |
 | llvm/test/CodeGen/Thumb2/mve-vcreate.ll |
 | llvm/test/CodeGen/Thumb2/mve-vst3.ll |
 | llvm/test/CodeGen/Thumb2/mve-pred-or.ll |
 | llvm/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll |
 | llvm/test/CodeGen/Thumb2/mve-vmulh.ll |
 | llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll |
 | llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll |
Commit
b88ed4ec8e7d35f786a59de527989316ba9c5f48
by nicolas.vasilache[mlir][Linlag] Reflow Linalg.md - NFC
Markdown formatting seems to now be available, reflowing the doc without changing any content.
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 | mlir/docs/Dialects/Linalg.md |
Commit
22c1bd57bf34391cd16e91fa4830dba4cdf17aa2
by i[ELF] Rename R_TLS to R_TPREL and R_NEG_TLS to R_TPREL_NEG. NFC
The scope of R_TLS (TP offset relocation types (TPREL/TPOFF) used for the local-exec TLS model) is actually narrower than its name may imply. R_TLS_NEG is only used by Solaris R_386_TLS_LE_32.
Rename them so that they will be less confusing.
Reviewed By: grimar, psmith, rprichard
Differential Revision: https://reviews.llvm.org/D93467
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 | lld/ELF/Arch/PPC64.cpp |
 | lld/ELF/Relocations.h |
 | lld/ELF/Arch/AArch64.cpp |
 | lld/ELF/Arch/X86_64.cpp |
 | lld/ELF/Relocations.cpp |
 | lld/ELF/Arch/ARM.cpp |
 | lld/ELF/Arch/X86.cpp |
 | lld/ELF/Arch/PPC.cpp |
 | lld/ELF/Arch/RISCV.cpp |
 | lld/ELF/Arch/Hexagon.cpp |
 | lld/ELF/Arch/SPARCV9.cpp |
 | lld/ELF/Arch/Mips.cpp |
 | lld/ELF/InputSection.cpp |