SuccessChanges

Summary

  1. [RISCV] Add intrinsics for vsetvli instruction (details)
  2. Rename files with same (case insensitive) name (details)
  3. [RISCV] Assume no-op addrspacecasts by default (details)
Commit 69c8d121f7f22e483e35a3d893052011ee70c23e by craig.topper
[RISCV] Add intrinsics for vsetvli instruction

This patch adds two IR intrinsics for vsetvli instruction. One to set the vector length to a user specified value and one to set it to vlmax. The vlmax uses the X0 source register encoding.

Clang builtins will follow in a separate patch

Differential Revision: https://reviews.llvm.org/D92973
The file was modifiedllvm/include/llvm/IR/IntrinsicsRISCV.td
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
The file was addedllvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Commit 08c4b4054b3ded660fc87ccbaa9a6bc4e390f6ff by chih-ping.chen
Rename files with same (case insensitive) name

Patch by: Aditya Kumar.

Differential Revision: https://reviews.llvm.org/D93559
The file was addedllvm/test/DebugInfo/X86/dimodule-external-fortran.ll
The file was removedllvm/test/DebugInfo/X86/dimodule.ll
Commit d4ed253d0b8487d9e9fd95a3895f83c437e5e7bb by fraser
[RISCV] Assume no-op addrspacecasts by default

To support OpenCL, which typically uses SPIR as an IR, non-zero address
spaces must be accounted for. This patch makes the RISC-V target assume
no-op address space casts across the board, which effectively removes
the need to support addrspacecast instructions in the backend.

For a RISC-V implementation with different configurations or specialized
address spaces where casts aren't no-ops, the function can be adjusted
as required.

Reviewed By: jrtc27

Differential Revision: https://reviews.llvm.org/D93536
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetMachine.h
The file was addedllvm/test/CodeGen/RISCV/addrspacecast.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetMachine.cpp