SuccessChanges

Summary

  1. [VE] Optimize LEA combinations (details)
  2. Refactoring the attribute plugin example to fit the new API (details)
  3. [Statepoints] Disable VReg lowering for values used on exception path of invoke. (details)
  4. [VPlan] Make VPRecipeBase inherit from VPDef. (details)
  5. [VE] Correct VMP allocation in calling conv (details)
  6. [InstSimplify] add tests for inverted logic operands; NFC (details)
  7. [InstSimplify] reduce logic with inverted add/sub ops (details)
Commit a3a896d1cdc0fd2f87de4787120eaac08e69eb5f by marukawa
[VE] Optimize LEA combinations

Change to optimize references of elements of aggregate data.  Also
add regression tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D93627
The file was addedllvm/test/CodeGen/VE/Scalar/lea-opt.ll
The file was modifiedllvm/lib/Target/VE/VEInstrInfo.td
Commit b2ba6867eac10874bd279c739639bdb9e60c1996 by aaron
Refactoring the attribute plugin example to fit the new API

Make the example compile and the test case pass.
The file was modifiedclang/examples/Attribute/Attribute.cpp
The file was modifiedclang/test/Frontend/plugin-attribute.cpp
Commit 6f45049fb6e5c6d573ef5bae338da822f6cbaa53 by dantrushin
[Statepoints] Disable VReg lowering for values used on exception path of invoke.

Currently we lower invokes the same way as usual calls, e.g.:

V1 = STATEPOINT ... V (tied-def 0)

But this is incorrect is V1 is used on exceptional path.
By LLVM rules V1 neither dominates its uses in landing pad, nor
its live range is live on entry to landing pad. So compiler is
allowed to do various weird transformations like splitting live
range after statepoint and use split LR in catch block.

Until (and if) we find better solution to this problem, let's
use old lowering (spilling) for those values which are used on
exceptional path and allow VReg lowering for values used only
on normal path.

Differential Revision: https://reviews.llvm.org/D93449
The file was modifiedllvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/statepoint-vreg-invoke.ll
Commit f25089237376dd43c8c37a18ea9d132f0845eda4 by flo
[VPlan] Make VPRecipeBase inherit from VPDef.

This patch makes VPRecipeBase a direct subclass of VPDef, moving the
SubclassID to VPDef.

Reviewed By: gilr

Differential Revision: https://reviews.llvm.org/D90564
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanValue.h
The file was modifiedllvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Commit 8c2ad9e85f677546021880dc88e24f633ccacd93 by marukawa
[VE] Correct VMP allocation in calling conv

VE used to allocate VM1, VM2, VMP2 (VM4+VM5), and VM3.  This patch
corrects to allocate VM1, VM2, VMP2 (VM4+VM5), and VM6.  Also add
a regression test.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D93570
The file was modifiedllvm/lib/Target/VE/VECallingConv.td
The file was modifiedllvm/test/CodeGen/VE/Vector/fastcc_callee.ll
Commit d6118759f30e343a05aab053f66e5049ea149175 by spatel
[InstSimplify] add tests for inverted logic operands; NFC
The file was modifiedllvm/test/Transforms/InstSimplify/AndOrXor.ll
Commit 38ca7face67e8488d482b66a999d0a685806879f by spatel
[InstSimplify] reduce logic with inverted add/sub ops

https://llvm.org/PR48559
This could be part of a larger ValueTracking API,
but I don't see that currently.

https://rise4fun.com/Alive/gR0

  Name: and
  Pre: C1 == ~C2
  %sub = add i8 %x, C1
  %sub1 = sub i8 C2, %x
  %r = and i8 %sub, %sub1
  =>
  %r = 0

  Name: or
  Pre: C1 == ~C2
  %sub = add i8 %x, C1
  %sub1 = sub i8 C2, %x
  %r = or i8 %sub, %sub1
  =>
  %r = -1

  Name: xor
  Pre: C1 == ~C2
  %sub = add i8 %x, C1
  %sub1 = sub i8 C2, %x
  %r = xor i8 %sub, %sub1
  =>
  %r = -1
The file was modifiedllvm/test/Transforms/InstSimplify/AndOrXor.ll
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp