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Summary

  1. VirtRegMap: Use Register (details)
  2. AMDGPU: Fix assert when checking for implicit operand legality (details)
  3. [RISCV] Add intrinsics for vslide1up/down, vfslide1up/down instruction (details)
  4. [RISCV] Add intrinsics for vwmacc[u|su|us] instructions (details)
Commit 5bec0828347893544ab863ddf4caa2f0b5ef79dd by Matthew.Arsenault
VirtRegMap: Use Register
The file was modifiedllvm/include/llvm/CodeGen/VirtRegMap.h
The file was modifiedllvm/lib/CodeGen/LiveRangeEdit.cpp
Commit 29ed846d671117b9a635767dac43cb19fb5ce11f by Matthew.Arsenault
AMDGPU: Fix assert when checking for implicit operand legality
The file was modifiedllvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
Commit c8874464b5f63e300bb7507340c04801e033c02e by shihpo.hung
[RISCV] Add intrinsics for vslide1up/down, vfslide1up/down instruction

This patch adds intrinsics for vslide1up, vslide1down, vfslide1up, vfslide1down.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>

Differential Revision: https://reviews.llvm.org/D93608
The file was addedllvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsRISCV.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll
Commit 42687839980308bbed8fe909b9810a0fb48f9813 by shihpo.hung
[RISCV] Add intrinsics for vwmacc[u|su|us] instructions

This patch defines vwmacc[u|su|us] intrinsics and lower to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>

Differential Revision: https://reviews.llvm.org/D93675
The file was addedllvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsRISCV.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td