Changes

Summary

[RISCV] Add intrinsics for vf[n]macc/vf[n]msac/vf[n]madd/vf[n]msub instructions (details)
AMDGPU: Add spilled CSR SGPRs to entry block live ins (details)
AMDGPU: Use Register (details)
[lld/mac] Add --version flag (details)
GlobalISel: Return APInt from getConstantVRegVal (details)

Commit ad0a7ad950fec5e422e84f0d3f8942d5e1b116f6 by shihpo.hung [RISCV] Add intrinsics for vf[n]macc/vf[n]msac/vf[n]madd/vf[n]msub instructions This patch defines vfmadd/vfnmacc, vfmsac/vfnmsac, vfmadd/vfnmadd, and vfmsub/vfnmsub lower to V instructions. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com> Differential Revision: https://reviews.llvm.org/D93691
	llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll
	llvm/include/llvm/IR/IntrinsicsRISCV.td
	llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll
	llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll
	llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll
	llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll
	llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll
	llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll
	llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
	llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll
	llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll
	llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll
	llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll
	llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll
	llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll
	llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll
	llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll
	llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll
Commit bac54639c7be602cabffcc3b801316f784f1c4b1 by Matthew.Arsenault AMDGPU: Add spilled CSR SGPRs to entry block live ins
	llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
	llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
Commit 8bf9cdeaee4834bcba35322f1d84c57c691d2244 by Matthew.Arsenault AMDGPU: Use Register
	llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
Commit 77fb45e59e49d25fbc57854b62599ae24aa2c4c9 by thakis [lld/mac] Add --version flag It's an extension to ld64, but all the other ports have it, and someone asked for it in PR43721. While here, change the COFF help text to match the other ports. Differential Revision: https://reviews.llvm.org/D93491
	lld/MachO/Driver.cpp
	lld/COFF/Options.td
	lld/test/MachO/driver.test
	lld/MachO/Options.td
Commit 581d13f8aeb66c040d5ea69ad4385f766e1f97c9 by Matthew.Arsenault GlobalISel: Return APInt from getConstantVRegVal Returning int64_t was arbitrarily limiting for wide integer types, and the functions should handle the full generality of the IR. Also changes the full form which returns the originally defined vreg. Add another wrapper for the common case of just immediately converting to int64_t (arguably this would be useful for the full return value case as well). One possible issue with this change is some of the existing uses did break without conversion to getConstantVRegSExtVal, and it's possible some without adequate test coverage are now broken.
	llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
	llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
	llvm/lib/CodeGen/GlobalISel/Utils.cpp
	llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
	llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
	llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
	llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
	llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
	llvm/include/llvm/CodeGen/GlobalISel/Utils.h
	llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
	llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
	llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
	llvm/lib/Target/X86/X86InstructionSelector.cpp