[RISCV] Pattern-match more vector-splatted constants (details)
[RISCV] Pattern-match more vector-splatted constants
This patch extends the pattern-matching capability of vector-splatted constants. When illegally-typed constants are legalized they are canonically sign-extended to XLenVT. This preserves the sign and allows us to match simm5. If they were zero-extended for whatever reason we'd lose that ability: e.g. `(i8 -1) -> (XLenVT 255)` would not be matched under the current logic.
To address this we first manually sign-extend the splatted constant from the vector element type to int64_t. This preserves the semantics while removing any implicitly-truncated bits.
The corresponding logic for uimm5 was not updated, the rationale being that neither sign- nor zero-extending a legal uimm5 immediate should change that (unless we expect actual "garbage" upper bits).