Changes

Summary

Commit 8b67c98c4774313ab0ce5db1a975d2e69850368a by aqjune [UpdateTestChecks] Fix update_analyze_test_checks.py failure
	llvm/utils/update_analyze_test_checks.py
Commit f3f9ce3b7948b250bc532818ed76a64cea8b6fbe by zakk.chen [RISCV] Define vmclr.m/vmset.m intrinsics. Define vmclr.m/vmset.m intrinsics and lower to vmxor.mm/vmxnor.mm. Ideally all rvv pseudo instructions could be implemented in C header, but those two instructions don't take an input, codegen can not guarantee that the source register becomes the same as the destination. We expand pseduo-v-inst into corresponding v-inst in RISCVExpandPseudoInsts pass. Reviewed By: craig.topper, frasercrmck Differential Revision: https://reviews.llvm.org/D93849
	llvm/include/llvm/IR/IntrinsicsRISCV.td
	llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
	llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll
	llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
	llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll
	llvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll
	llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll