SuccessChanges

Summary

  1. [MSSAUpdater] Skip renaming when inserting def in unreachable block. (details)
  2. [NewPM][AMDGPU] Port amdgpu-lower-kernel-attributes (details)
  3. [RISCV] Don't use tail agnostic policy on instructions where destination is tied to source (details)
  4. [IROutliner] Adding a cost model, and debug option to turn the model off. (details)
Commit b980bed34b96a9a85c256b1627ef9339d82829eb by flo
[MSSAUpdater] Skip renaming when inserting def in unreachable block.

This fixes a updater crash when moving memory defs between unreachable
blocks.

Fixes PR48616.
The file was modifiedllvm/test/Transforms/GVN/preserve-memoryssa.ll
The file was modifiedllvm/lib/Analysis/MemorySSAUpdater.cpp
Commit 7ecbe0c7a01848fce88dcf3b6977cec866e9938b by aeubanks
[NewPM][AMDGPU] Port amdgpu-lower-kernel-attributes

And add it to the AMDGPU opt pipeline.

This is a function pass instead of a module pass (like the legacy pass)
because it's getting added to a CGSCCPassManager, and you can't put a
module pass in a CGSCCPassManager.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D93885
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.h
The file was modifiedllvm/tools/opt/opt.cpp
Commit 79cbb003c53009e5ca35b804bb7655dba97776e7 by craig.topper
[RISCV] Don't use tail agnostic policy on instructions where destination is tied to source

If the destination is tied, then user has some control of the
register used for input. They would have the ability to control
the value of any tail elements. By using tail agnostic we take
this option away from them.

Its not clear that the intrinsics are defined such that this isn't
supposed to work. And undisturbed is a valid implementation for agnostic
so code wouldn't even fail to work on all systems if we always used
agnostic.

The vcompress intrinsic is defined to require tail undisturbed so
at minimum we need this for that instruction or need to redefine
the intrinsic.

I've made an exception here for vmv.s.x/fmv.s.f and reduction
instructions which only write to element 0 regardless of the tail
policy. This allows us to keep the agnostic policy on those which
should allow better redundant vsetvli removal.

An enhancement would be to check for undef input and keep the
agnostic policy, but we don't have good test coverage for that yet.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D93878
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/viota-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vand-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlxe-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll
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The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll
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The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll
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Commit 6df161a2fbf62bd4ab7297fe1fb234cdc972a48b by andrew.litteken
[IROutliner] Adding a cost model, and debug option to turn the model off.

This adds a cost model that takes into account the total number of
machine instructions to be removed from each region, the number of
instructions added by adding a new function with a set of instructions,
and the instructions added by handling arguments.

Tests not adding flags:

llvm/test/Transforms/IROutliner/outlining-cost-model.ll

Reviewers: jroelofs, paquette

Differential Revision: https://reviews.llvm.org/D87299
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The file was modifiedllvm/test/Transforms/IROutliner/illegal-memset.ll
The file was modifiedllvm/test/Transforms/IROutliner/outlining-same-output-blocks.ll
The file was modifiedllvm/test/Transforms/IROutliner/outlining-commutative-fp.ll