SuccessChanges

Summary

  1. [ASTMatchers] Ensure that we can match inside lambdas (details)
  2. [ASTMatchers] Fix build when no targets are enabled (details)
  3. [X86][AVX] combineVectorSignBitsTruncation - use PACKSS/PACKUS in more AVX cases (details)
  4. [VPlan] Re-add interleave group members to plan. (details)
Commit c3a21e5de3dc3f55e4d219afd55dec518159d356 by steveire
[ASTMatchers] Ensure that we can match inside lambdas

Because we don't know in ASTMatchFinder whether we're matching in AsIs
or IgnoreUnlessSpelledInSource mode, we need to traverse the lambda
twice, but store whether we're matching in nodes spelled in source or
not.

Differential Revision: https://reviews.llvm.org/D93688
The file was modifiedclang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
The file was modifiedclang/lib/ASTMatchers/ASTMatchFinder.cpp
The file was modifiedclang/lib/ASTMatchers/ASTMatchersInternal.cpp
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchersInternal.h
Commit c3403dc63d73710d14844e8a8cfad7a0f52d4a54 by steveire
[ASTMatchers] Fix build when no targets are enabled

This makes sense to do when building only tools like clang-tidy for
example.

Differential Revision: https://reviews.llvm.org/D93987
The file was modifiedllvm/cmake/modules/LLVM-Config.cmake
Commit 73a44f437bf19ecf2c865e6c8b9b8a2e4a811960 by llvm-dev
[X86][AVX] combineVectorSignBitsTruncation - use PACKSS/PACKUS in more AVX cases

AVX512 has fast truncation ops, but if the truncation source is a concatenation of subvectors then its likely that we can use PACK more efficiently.

This is only guaranteed to work for truncations to 128/256-bit vectors as the PACK works across 128-bit sub-lanes, for now I've just disabled 512-bit truncation cases but we need to get them working eventually for D61129.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-pack-128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-pack-256.ll
Commit 8a47e6252ad43a2eb3238f9b36394571ba13f4a9 by flo
[VPlan] Re-add interleave group members to plan.

Creating in-loop reductions relies on IR references to map
IR values to VPValues after interleave group creation.

Make sure we re-add the updated member to the plan, so the look-ups
still work as expected

This fixes a crash reported after D90562.
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp