SuccessChanges

Summary

  1. [flang][driver] Copy input files into a temp dir when testing (details)
  2. [mlir][linalg] Support parsing attributes in named op spec (details)
  3. [mlir][linalg] Support permutation when lowering to loop nests (details)
  4. [DAGCombiner] Use getVectorElementCount inside visitINSERT_SUBVECTOR (details)
Commit 8298ec2d6299a95d2920cb8ee993ac6c5e604097 by andrzej.warzynski
[flang][driver] Copy input files into a temp dir when testing

The following frontend driver invocation will generate 2 output files
in the same directory as the input files:
```
flang-new -fc1 input-1.f input-2.f
```
This is the desired behaviour. However, when testing we need to make
sure that we don't pollute the source directory. To this end, copy test
input files into a temporary directory.

Differential Revision: https://reviews.llvm.org/D94243
The file was modifiedflang/test/Frontend/multiple-input-files.f90
Commit df86f15f0c53c395dac5a14aba08745bc12b9b9b by antiagainst
[mlir][linalg] Support parsing attributes in named op spec

With this, now we can specify a list of attributes on named ops
generated from the spec. The format is defined as

```
attr-id ::= bare-id (`?`)?
attr-typedef ::= type (`[` `]`)?
attr-def ::= attr-id `:` attr-typedef

tc-attr-def ::= `attr` `(` attr-def-list `)`
tc-def ::= `def` bare-id
  `(`tensor-def-list`)` `->` `(` tensor-def-list`)`
  (tc-attr-def)?
```

For example,

```
ods_def<SomeCppOp>
def some_op(...) -> (...)
attr(
  f32_attr: f32,
  i32_attr: i32,
  array_attr : f32[],
  optional_attr? : f32
)
```

where `?` means optional attribute and `[]` means array type.

Reviewed By: hanchung, nicolasvasilache

Differential Revision: https://reviews.llvm.org/D94240
The file was modifiedmlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
The file was modifiedmlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
Commit 55225471d9838e452cfb31e0edae6162b7226221 by antiagainst
[mlir][linalg] Support permutation when lowering to loop nests

Linalg ops are perfect loop nests. When materializing the concrete
loop nest, the default order specified by the Linalg op's iterators
may not be the best for further CodeGen: targets frequently need
to plan the loop order in order to gain better data access. And
different targets can have different preferences. So there should
exist a way to control the order.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D91795
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Loops.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
The file was modifiedmlir/include/mlir/Dialect/Linalg/Passes.td
The file was addedmlir/test/Dialect/Linalg/loop-order.mlir
Commit 007358239decd45819a6fa44eb2a2e07fd85e796 by joe.ellis
[DAGCombiner] Use getVectorElementCount inside visitINSERT_SUBVECTOR

This avoids TypeSize-/ElementCount-related warnings.

Differential Revision: https://reviews.llvm.org/D92747
The file was addedllvm/test/CodeGen/AArch64/dag-combine-insert-subvector.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp