SuccessChanges

Summary

  1. [tools] Mark output of tools as text if it is really text (details)
  2. [NFC] Disallow unused prefixes under llvm/test/CodeGen (details)
  3. [mlir][vector] Add side-effect information to different load/store ops (details)
  4. Enable python bindings for tensor, shape and linalg dialects. (details)
  5. [mlir][CAPI] Introduce standard source layout for mlir-c dialect registration. (details)
  6. Revert "[mlir][linalg] Support parsing attributes in named op spec" (details)
  7. [InstCombine] reduce icmp(ashr X, C1), C2 to sign-bit test (details)
  8. [GlobalISel] Map extractelt to G_EXTRACT_VECTOR_ELT (details)
  9. [libc][NFC] Make __support/common.h an in tree header. (details)
  10. [c++20] Don't consider string literal operator templates for numeric (details)
  11. Add an assert to CGDebugInfo::getTypeOrNull (details)
  12. [RISCV] Add scalable vector fadd/fsub/fmul/fdiv ISel patterns (details)
  13. [mlir][vector] verify memref of vector memory ops (details)
  14. [PredicateInfo] Add test for one unknown condition in and/or (NFC) (details)
  15. [SCCP] Fix misclassified conditions in test (NFC) (details)
  16. CGDebugInfo: Delete unused parameters (details)
Commit 8ad998a6115a8cd59a18ebdd5ec65329e42050e7 by Abhina.Sreeskantharajan
[tools] Mark output of tools as text if it is really text

This is a continuation of https://reviews.llvm.org/D67696. The following tools also need to set the OF_Text flag correctly.

  -   llvm-profdata
  -   llvm-link

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D94313
The file was modifiedllvm/test/tools/llvm-profdata/csprof-dump.test
The file was modifiedllvm/test/tools/llvm-profdata/instr-remap.test
The file was modifiedllvm/tools/llvm-link/llvm-link.cpp
The file was modifiedllvm/tools/llvm-profdata/llvm-profdata.cpp
Commit 05e90cefeb4bc5613b2cadedc2b8e2ecb2ed20ed by mtrofin
[NFC] Disallow unused prefixes under llvm/test/CodeGen

This patch finishes addressing unused prefixes under CodeGen: 2
remaining tests fixed, and then undo-ing the lit.local.cfg changes under
various subdirs and moving the policy under CodeGen.

Differential Revision: https://reviews.llvm.org/D94430
The file was modifiedllvm/test/CodeGen/ARM/speculation-hardening-sls.ll
The file was modifiedllvm/test/CodeGen/NVPTX/f16-instructions.ll
The file was modifiedllvm/test/CodeGen/X86/lit.local.cfg
The file was modifiedllvm/test/CodeGen/AMDGPU/lit.local.cfg
The file was modifiedllvm/test/CodeGen/PowerPC/lit.local.cfg
The file was addedllvm/test/CodeGen/lit.local.cfg
Commit c1ae378205db72cd80a52b85b8474077d1aa5b15 by thomasraoux
[mlir][vector] Add side-effect information to different load/store ops

Differential Revision: https://reviews.llvm.org/D94434
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
The file was modifiedmlir/test/Dialect/Vector/canonicalize.mlir
Commit 53c866c286a7ca52bd09c7661d4c532ce5c0def8 by stellaraccident
Enable python bindings for tensor, shape and linalg dialects.

* We've got significant missing features in order to use most of these effectively (i.e. custom builders, region-based builders).
* We presently also lack a mechanism for actually registering these dialects but they can be use with contexts that allow unregistered dialects for further prototyping.

Differential Revision: https://reviews.llvm.org/D94368
The file was modifiedmlir/lib/Bindings/Python/CMakeLists.txt
The file was modifiedmlir/cmake/modules/AddMLIRPythonExtension.cmake
The file was addedmlir/lib/Bindings/Python/TensorOps.td
The file was addedmlir/lib/Bindings/Python/LinalgOps.td
The file was modifiedmlir/test/Bindings/Python/CMakeLists.txt
The file was addedmlir/lib/Bindings/Python/ShapeOps.td
Commit cceb1bfcbbc4ee2e9cc56b76a4acc4cd52968791 by stellaraccident
[mlir][CAPI] Introduce standard source layout for mlir-c dialect registration.

* Registers a small set of sample dialects.
* NFC with respect to existing C-API symbols but some headers have been moved down a level to the Dialect/ sub-directory.
* Adds an additional entry point per dialect that is needed for dynamic discovery/loading.
* See discussion: https://llvm.discourse.group/t/dialects-and-the-c-api/2306/16

Differential Revision: https://reviews.llvm.org/D94370
The file was removedmlir/lib/CAPI/Standard/StandardDialect.cpp
The file was removedmlir/lib/CAPI/Standard/CMakeLists.txt
The file was addedmlir/include/mlir-c/Dialect/Linalg.h
The file was addedmlir/lib/CAPI/Dialect/CMakeLists.txt
The file was removedmlir/include/mlir-c/StandardDialect.h
The file was addedmlir/lib/CAPI/Dialect/Tensor.cpp
The file was addedmlir/lib/CAPI/Dialect/Linalg.cpp
The file was addedmlir/lib/CAPI/Dialect/Shape.cpp
The file was addedmlir/include/mlir-c/Dialect/SCF.h
The file was addedmlir/include/mlir-c/Dialect/Standard.h
The file was addedmlir/include/mlir-c/Dialect/Tensor.h
The file was addedmlir/include/mlir/CAPI/Registration.h
The file was addedmlir/include/mlir-c/Dialect/Shape.h
The file was modifiedmlir/lib/CAPI/CMakeLists.txt
The file was modifiedmlir/test/CAPI/ir.c
The file was modifiedmlir/include/mlir-c/Registration.h
The file was addedmlir/lib/CAPI/Dialect/SCF.cpp
The file was addedmlir/lib/CAPI/Dialect/Standard.cpp
Commit 110775809ad114e190132290657a86b2c292a878 by joker.eph
Revert "[mlir][linalg] Support parsing attributes in named op spec"

This reverts commit df86f15f0c53c395dac5a14aba08745bc12b9b9b.

The gcc-5 build was broken by this change:

  mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp:1275:77:   required from here
  /usr/include/c++/5/ext/new_allocator.h:120:4: error: no matching function for call to 'std::pair<const std::__cxx11::basic_string<char>, {anonymous}::TCParser::RegisteredAttr>::pair(llvm::StringRef&, {anonymous}::TCParser::RegisteredAttr'
The file was modifiedmlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
The file was modifiedmlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
Commit 288f3fc5dfee0c51fc00fe10a985f93c505073eb by spatel
[InstCombine] reduce icmp(ashr X, C1), C2 to sign-bit test

This is a more basic pattern that we should handle before trying to solve:
https://llvm.org/PR48640

There might be a better way to think about this because the pre-condition
that I came up with (number of sign bits in the compare constant) misses a
potential transform for each of ugt and ult as commented on in the test file.

Tried to model this is in Alive:
https://rise4fun.com/Alive/juX1
...but I couldn't get the ComputeNumSignBits() pre-condition to work as
expected, so replaced with leading 0/1 preconditions instead.

  Name: ugt
  Pre: countLeadingZeros(C2) <= C1 && countLeadingOnes(C2) <= C1
  %a = ashr %x, C1
  %r = icmp ugt i8 %a, C2
    =>
  %r = icmp slt i8 %x, 0

  Name: ult
  Pre: countLeadingZeros(C2) <= C1 && countLeadingOnes(C2) <= C1
  %a = ashr %x, C1
  %r = icmp ult i4 %a, C2
    =>
  %r = icmp sgt i4 %x, -1

Also approximated in Alive2:
https://alive2.llvm.org/ce/z/u5hCcz
https://alive2.llvm.org/ce/z/__szVL

Differential Revision: https://reviews.llvm.org/D94014
The file was modifiedllvm/test/Transforms/InstCombine/icmp-shr.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
Commit 32c073acb320db3b22ca76b1e21dd688a70b50e8 by bjorn.a.pettersson
[GlobalISel] Map extractelt to G_EXTRACT_VECTOR_ELT

Before this patch there was generic mapping from vector_extract
to G_EXTRACT_VECTOR_ELT added in SelectionDAGCompat.td. That
mapping is now replaced by a mapping from extractelt instead.

The reasoning is that vector_extract is marked as deprecated,
so it is assumed that a majority of targets will use extractelt
and not vector_extract (and that the long term solution for all
targets would be to use extractelt).

Targets like AArch64 that still use vector_extract can add an
additional mapping from the deprecated vector_extract as target
specific tablegen definitions. Such a mapping is added for AArch64
in this patch to avoid breaking tests.

When adding the extractelt => G_EXTRACT_VECTOR_ELT mapping we
triggered some new code paths in GlobalISelEmitter, ending up in
an assert when trying to import a pattern containing EXTRACT_SUBREG
for ARM. Therefore this patch also adds a "failedImport" warning
for that situation (instead of hitting the assert).

Differential Revision: https://reviews.llvm.org/D93416
The file was modifiedllvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrGISel.td
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
Commit aefeb5f136e7b72b251ce2881cb39a1fe8f0d76a by sivachandra
[libc][NFC] Make __support/common.h an in tree header.

It was previously a generated header. It can easily converted to a
generated header if required in future.

Reviewed By: michaelrj

Differential Revision: https://reviews.llvm.org/D94445
The file was removedlibc/src/__support/common.h.def
The file was modifiedlibc/src/__support/CMakeLists.txt
The file was addedlibc/src/__support/common.h
Commit 9b222b108a2e37eb45d3156ec8554d148d658a8a by richard
[c++20] Don't consider string literal operator templates for numeric
literals.

A literal interpretation of the standard wording allows this, but it was
never intended that string literal operator templates would be used for
anything other than user-defined string literals.
The file was modifiedclang/test/SemaCXX/cxx2a-user-defined-literals.cpp
The file was modifiedclang/lib/Sema/SemaLookup.cpp
Commit f4cec703ec8452f9d8b04fae171ba459adf38123 by i
Add an assert to CGDebugInfo::getTypeOrNull
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
Commit 7989684a2e4a496201ff41d31cede764487ca80f by fraser
[RISCV] Add scalable vector fadd/fsub/fmul/fdiv ISel patterns

Original patch by @rogfer01.

This patch adds ISel patterns for the above operations to the
corresponding vector/vector and vector/scalar RVV instructions, as well
as extra patterns to match operand-swapped scalar/vector vfrsub and
vfrdiv.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Fraser Cormack <fraser@codeplay.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94408
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
The file was addedllvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv64.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv32.ll
Commit 046612d29d7894783e8fcecbc62ebd6b4a78499f by ajcbik
[mlir][vector] verify memref of vector memory ops

This ensures the memref base + indices expression is well-formed

Reviewed By: ThomasRaoux, ftynse

Differential Revision: https://reviews.llvm.org/D94441
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/test/Dialect/Vector/invalid.mlir
Commit a808d89d355c98d7475795e13271beb90e9436cb by nikita.ppv
[PredicateInfo] Add test for one unknown condition in and/or (NFC)

Test the case where one part of and/or is an icmp, while the other
one is an arbitrary value.
The file was modifiedllvm/test/Transforms/Util/PredicateInfo/testandor.ll
Commit 00f773cf424699d8eb31591fdc95e0ca18b2682c by nikita.ppv
[SCCP] Fix misclassified conditions in test (NFC)
The file was modifiedllvm/test/Transforms/SCCP/conditions-ranges.ll
Commit b88c8f1aab527f1aebe612ab6c50a418bff88584 by i
CGDebugInfo: Delete unused parameters
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
The file was modifiedclang/lib/CodeGen/CGDebugInfo.h
The file was modifiedclang/lib/CodeGen/CodeGenFunction.cpp