Changes

[tools] Mark output of tools as text if it is really text

This is a continuation of https://reviews.llvm.org/D67696. The following tools also need to set the OF_Text flag correctly.

  -   llvm-profdata
  -   llvm-link

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D94313

[NFC] Disallow unused prefixes under llvm/test/CodeGen

This patch finishes addressing unused prefixes under CodeGen: 2
remaining tests fixed, and then undo-ing the lit.local.cfg changes under
various subdirs and moving the policy under CodeGen.

Differential Revision: https://reviews.llvm.org/D94430

[mlir][vector] Add side-effect information to different load/store ops

Differential Revision: https://reviews.llvm.org/D94434

Enable python bindings for tensor, shape and linalg dialects.

* We've got significant missing features in order to use most of these effectively (i.e. custom builders, region-based builders).
* We presently also lack a mechanism for actually registering these dialects but they can be use with contexts that allow unregistered dialects for further prototyping.

Differential Revision: https://reviews.llvm.org/D94368

[mlir][CAPI] Introduce standard source layout for mlir-c dialect registration.

* Registers a small set of sample dialects.
* NFC with respect to existing C-API symbols but some headers have been moved down a level to the Dialect/ sub-directory.
* Adds an additional entry point per dialect that is needed for dynamic discovery/loading.
* See discussion: https://llvm.discourse.group/t/dialects-and-the-c-api/2306/16

Differential Revision: https://reviews.llvm.org/D94370

Revert "[mlir][linalg] Support parsing attributes in named op spec"

This reverts commit df86f15f0c53c395dac5a14aba08745bc12b9b9b.

The gcc-5 build was broken by this change:

  mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp:1275:77:   required from here
  /usr/include/c++/5/ext/new_allocator.h:120:4: error: no matching function for call to 'std::pair<const std::__cxx11::basic_string<char>, {anonymous}::TCParser::RegisteredAttr>::pair(llvm::StringRef&, {anonymous}::TCParser::RegisteredAttr'

[InstCombine] reduce icmp(ashr X, C1), C2 to sign-bit test

This is a more basic pattern that we should handle before trying to solve:
https://llvm.org/PR48640

There might be a better way to think about this because the pre-condition
that I came up with (number of sign bits in the compare constant) misses a
potential transform for each of ugt and ult as commented on in the test file.

Tried to model this is in Alive:
https://rise4fun.com/Alive/juX1
...but I couldn't get the ComputeNumSignBits() pre-condition to work as
expected, so replaced with leading 0/1 preconditions instead.

  Name: ugt
  Pre: countLeadingZeros(C2) <= C1 && countLeadingOnes(C2) <= C1
  %a = ashr %x, C1
  %r = icmp ugt i8 %a, C2
    =>
  %r = icmp slt i8 %x, 0

  Name: ult
  Pre: countLeadingZeros(C2) <= C1 && countLeadingOnes(C2) <= C1
  %a = ashr %x, C1
  %r = icmp ult i4 %a, C2
    =>
  %r = icmp sgt i4 %x, -1

Also approximated in Alive2:
https://alive2.llvm.org/ce/z/u5hCcz
https://alive2.llvm.org/ce/z/__szVL

Differential Revision: https://reviews.llvm.org/D94014

[GlobalISel] Map extractelt to G_EXTRACT_VECTOR_ELT

Before this patch there was generic mapping from vector_extract
to G_EXTRACT_VECTOR_ELT added in SelectionDAGCompat.td. That
mapping is now replaced by a mapping from extractelt instead.

The reasoning is that vector_extract is marked as deprecated,
so it is assumed that a majority of targets will use extractelt
and not vector_extract (and that the long term solution for all
targets would be to use extractelt).

Targets like AArch64 that still use vector_extract can add an
additional mapping from the deprecated vector_extract as target
specific tablegen definitions. Such a mapping is added for AArch64
in this patch to avoid breaking tests.

When adding the extractelt => G_EXTRACT_VECTOR_ELT mapping we
triggered some new code paths in GlobalISelEmitter, ending up in
an assert when trying to import a pattern containing EXTRACT_SUBREG
for ARM. Therefore this patch also adds a "failedImport" warning
for that situation (instead of hitting the assert).

Differential Revision: https://reviews.llvm.org/D93416

[libc][NFC] Make __support/common.h an in tree header.

It was previously a generated header. It can easily converted to a
generated header if required in future.

Reviewed By: michaelrj

Differential Revision: https://reviews.llvm.org/D94445

[c++20] Don't consider string literal operator templates for numeric
literals.

A literal interpretation of the standard wording allows this, but it was
never intended that string literal operator templates would be used for
anything other than user-defined string literals.

Add an assert to CGDebugInfo::getTypeOrNull

[RISCV] Add scalable vector fadd/fsub/fmul/fdiv ISel patterns

Original patch by @rogfer01.

This patch adds ISel patterns for the above operations to the
corresponding vector/vector and vector/scalar RVV instructions, as well
as extra patterns to match operand-swapped scalar/vector vfrsub and
vfrdiv.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Fraser Cormack <fraser@codeplay.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94408

[mlir][vector] verify memref of vector memory ops

This ensures the memref base + indices expression is well-formed

Reviewed By: ThomasRaoux, ftynse

Differential Revision: https://reviews.llvm.org/D94441

[PredicateInfo] Add test for one unknown condition in and/or (NFC)

Test the case where one part of and/or is an icmp, while the other
one is an arbitrary value.

[SCCP] Fix misclassified conditions in test (NFC)

CGDebugInfo: Delete unused parameters