1. [NFC] Rename ThinLTOPhase to ThinOrFullLTOPhase and move it from PassBuilder.h (details)
  2. [SystemZ]  Clear Available set in SystemZPostRASchedStrategy::initialize(). (details)
  3. [libunwind] Unwind through aarch64/Linux sigreturn frame (details)
  4. [flang] Add tests for procedure arguments with implicit interfaces (details)
  5. [RISCV] Custom lower ISD::VSCALE. (details)
Commit 86341247c4a2ffa4328945b03e7a05b1c51c3889 by wmi
[NFC] Rename ThinLTOPhase to ThinOrFullLTOPhase and move it from PassBuilder.h
to Pass.h.

In some compiler passes like SampleProfileLoaderPass, we want to know which
LTO/ThinLTO phase the pass is in. Currently the phase is represented in enum
class PassBuilder::ThinLTOPhase, so it is only available in PassBuilder and
it also cannot represent phase in full LTO. The patch extends it to include
full LTO phases and move it from PassBuilder.h to Pass.h, then it is much
easier for PassBuilder to communiate with each pass about current LTO phase.

Differential Revision:
The file was modifiedpolly/lib/Support/RegisterPasses.cpp
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/lib/Passes/PassRegistry.def
The file was modifiedllvm/lib/Transforms/IPO/SampleProfile.cpp
The file was modifiedllvm/include/llvm/Pass.h
The file was modifiedllvm/include/llvm/Transforms/IPO/SampleProfile.h
The file was modifiedllvm/include/llvm/Passes/PassBuilder.h
Commit ddd03842c3472fedf164274c479272089c426ee5 by paulsson
[SystemZ]  Clear Available set in SystemZPostRASchedStrategy::initialize().

This needs to be done in order to not crash with -misched-cutoff.


Review: Ulrich Weigand

Differential Revision:
The file was addedllvm/test/CodeGen/SystemZ/misched-cutoff.ll
The file was modifiedllvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
Commit c82deed6764cbc63966374baf9721331901ca958 by rprichard
[libunwind] Unwind through aarch64/Linux sigreturn frame

An AArch64 sigreturn trampoline frame can't currently be described
in a DWARF .eh_frame section, because the AArch64 DWARF spec currently
doesn't define a constant for the PC register. (PC and LR may need to
be restored to different values.)

Instead, use the same technique as libgcc or and
detect the sigreturn frame by looking for the sigreturn instructions:

    mov x8, #0x8b
    svc #0x0

If a sigreturn frame is detected, libunwind restores all the GPRs by
assuming that sp points at an rt_sigframe Linux kernel struct. This
behavior is a fallback mode that is only used if there is no ordinary
unwind info for sigreturn.

If libunwind can't find unwind info for a PC, it assumes that the PC is
readable, and would crash if it isn't. This could happen if:
- The PC points at a function compiled without unwind info, and which
   is part of an execute-only mapping (e.g. using -Wl,--execute-only).
- The PC is invalid and happens to point to unreadable or unmapped

In the tests, ignore a failed dladdr call so that the tests can run on
user-mode qemu for AArch64, which uses a stack-allocated trampoline
instead of a vDSO.

Reviewed By: danielkiss, compnerd, #libunwind

Differential Revision:
The file was modifiedlibunwind/include/__libunwind_config.h
The file was modifiedlibunwind/test/unwind_leaffunction.pass.cpp
The file was modifiedlibunwind/test/signal_unwind.pass.cpp
The file was modifiedlibunwind/src/UnwindCursor.hpp
Commit 3de92ca78cd4e180920acc077452f87c44c7d935 by psteinfeld
[flang] Add tests for procedure arguments with implicit interfaces

It's possible to declare an external procedure and then pass it as an
actual argument to a subprogram expecting a procedure argument.  I added
tests for this and added an error message to distinguish passing an
actual argument with an implicit interface from passing an argument with
a mismatched explicit interface.

Differential Revision:
The file was modifiedflang/test/Semantics/call09.f90
The file was modifiedflang/lib/Semantics/check-call.cpp
Commit dfc1901d513e1c5b9472d9b3403ca991b3d4a232 by craig.topper
[RISCV] Custom lower ISD::VSCALE.

This patch custom lowers ISD::VSCALE into a csrr vlenb followed
by a shift right by 3 followed by a multiply by the scale amount.

I've added computeKnownBits support to indicate that the csrr vlenb
always produces 3 trailng bits of 0s so the shift right is "exact".
This allows the shift and multiply sequence to be nicely optimized
into a single shift or removed completely when the scale amount is
a power of 2.

The non power of 2 case multiplying by 24 is still producing
suboptimal code. We could remove the right shift and use a
multiply by 3. Hopefully we can improve DAG combine to fix that
since it's not unique to this sequence.

This replaces D94144.

Reviewed By: HsiangKai

Differential Revision:
The file was addedllvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVMCInstLower.cpp
The file was modifiedllvm/lib/Target/RISCV/