Commit
555a395f2ccd531159538668fa36c7dc63ecff60
by nicolas.vasilache[mlir] NFC - Fix unused variable in non-debug mode
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 | mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOpsInterface.td |
Commit
6afdf13ae4ccf00296065960a0b311c87e6f8dd5
by iMakefile.rules: Avoid redundant .d generation (make restart) and inline archive rule to the only test
Take an example when `CXX_SOURCES` is main.cpp.
main.d is an included file. make will rebuild main.d, re-executes itself [1] to read in the new main.d file, then rebuild main.o, finally link main.o into a.out. main.cpp is parsed twice in this process.
This patch merges .d generation into .o generation [2], writes explicit rules for .c/.m and deletes suffix rules for %.m and %.o. Since a target can be satisfied by either of .c/.cpp/.m/.mm, we use multiple pattern rules. The rule with the prerequisite (with VPATH considered) satisfied is used [3].
Since suffix rules are disabled, the implicit rule for archive member targets is no long available [4]. Rewrite, simplify the archive rule and inline it into the only test `test/API/functionalities/archives/Makefile`.
[1]: https://www.gnu.org/software/make/manual/html_node/Remaking-Makefiles.html [2]: http://make.mad-scientist.net/papers/advanced-auto-dependency-generation/ [3]: https://www.gnu.org/software/make/manual/html_node/Pattern-Match.html [4]: https://www.gnu.org/software/make/manual/html_node/Archive-Update.html
ObjC/ObjCXX tests only run on macOS. I don't have testing environment. Hope someone can do it for me.
Reviewed By: JDevlieghere
Differential Revision: https://reviews.llvm.org/D94890
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 | lldb/packages/Python/lldbsuite/test/make/Makefile.rules |
 | lldb/test/API/functionalities/archives/Makefile |
Commit
045d84f4e6d7d6bbccaa6d965669a068fc329809
by david.greenD94954: Fixes Snapdragon Kryo CPU core detection
All of these families were claiming to be a73 based, which was causing -mcpu/mtune=native to never use the newer features available to these cores.
Goes through each and bumps the individual cores to their respective Big counterparts. Since this code path doesn't support big.little detection, there was already a precedent set with the Qualcomm line to choose the big cores only.
Adds a comment on each line for the product's name that the part number refers to. Confirmed on-device and through Linux header naming convections.
Additionally newer SoCs mix CPU implementer parts from multiple implementers. Both 0x41 (ARM) and 0x51 (Qualcomm) in the Snapdragon case
This was causing a desync in information where the scan at the start to find the implementer would mismatch the part scan later on. Now scan for both implementer and part at the start so these stay in sync.
Differential Revision: https://reviews.llvm.org/D94954
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 | llvm/lib/Support/Host.cpp |
 | llvm/unittests/Support/Host.cpp |
Commit
5959c28f24856f3d4a1db6b4743c66bdc6dcd735
by ajcbik[mlir][sparse] add asserts on reading in tensor data
Rationale: Since I made the argument that metadata helps with extra verification checks, I better actually do that ;-)
Reviewed By: penpornk
Differential Revision: https://reviews.llvm.org/D95072
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 | mlir/lib/ExecutionEngine/SparseUtils.cpp |
Commit
735a07f0478566f6f7c60a8a98eb8884db574113
by diego.caballeroRevert "[mlir][Affine] Add support for multi-store producer fusion"
This reverts commit 7dd198852b4db52ae22242dfeda4eccda83aa8b2.
ASAN issue.
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 | mlir/include/mlir/Analysis/Utils.h |
 | mlir/include/mlir/Transforms/LoopFusionUtils.h |
 | mlir/include/mlir/Analysis/AffineStructures.h |
 | mlir/lib/Analysis/AffineStructures.cpp |
 | mlir/lib/Transforms/LoopFusion.cpp |
 | mlir/include/mlir/Transforms/Passes.td |
 | mlir/lib/Analysis/Utils.cpp |
 | mlir/lib/Transforms/Utils/LoopFusionUtils.cpp |
 | mlir/test/Transforms/loop-fusion.mlir |
Commit
0f8386c4f6aa804fe43814fcb3ae29d271da82d7
by craig.topper[RISCV] Add addu.w and slliu.w test that uses getelementptr with zero extended indices.
This is closer to the kind of code that these intrinsics are targeted at. Note we fail to match slliu.w here because our pattern looks for (and (shl X, C1), 0xffffffff << C1) rather than (shl (and X, 0xffffffff), C1). I'll fix this in a follow up commit.
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 | llvm/test/CodeGen/RISCV/rv64Zbb.ll |
Commit
e996f1d4194bccf1c8ca984d695b848c0093bc23
by craig.topper[RISCV] Add another isel pattern for slliu.w.
Previously we only matched (and (shl X, C1), 0xffffffff << C1) which matches the InstCombine canonicalization order. But its possible to see (shl (and X, 0xffffffff), C1) if the pattern is introduced in SelectionDAG. For example, through expansion of a GEP.
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 | llvm/test/CodeGen/RISCV/rv64Zbb.ll |
 | llvm/lib/Target/RISCV/RISCVInstrInfoB.td |