SuccessChanges

Summary

  1. Reland [lldb] Fix TestThreadStepOut.py after "Flush local value map on every instruction" (details)
  2. [DAG] SimplifyDemandedBits - correctly adjust truncated shift amount type (details)
  3. [X86][SSE] Add uitofp(trunc(and(lshr(x,c)))) vector test (details)
  4. Add log1p lowering from standard to NVVM intrinsics (details)
  5. [DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE (REAPPLIED). (details)
  6. Add log1p lowering from standard to ROCDL intrinsics (details)
  7. [MC] Use std::make_tuple to make some toolchains happy again (details)
  8. [InstCombine] avoid crashing on attribute propagation (details)
  9. [clang][AST] Add get functions for CXXFoldExpr paren locations. (details)
  10. [lldb][NFC] Fix build with GCC<6 (details)
  11. AMDGPU: Add occupancy to serialized MachineFunctionInfo (details)
Commit ed2853d2c82d7286ba510c8f65049d6f649017f0 by Raphael Isemann
Reland [lldb] Fix TestThreadStepOut.py after "Flush local value map on every instruction"

The original patch got reverted as a dependency of cf1c774d6ace59c5adc9ab71b31e .
That patch got relanded so it's also necessary to reland this patch.

Original summary:

After cf1c774d6ace59c5adc9ab71b31e762c1be695b1, Clang seems to generate code
that is more similar to icc/Clang, so we can use the same line numbers for
all compilers in this test.
The file was modifiedlldb/test/API/functionalities/thread/step_out/TestThreadStepOut.py
The file was modifiedlldb/test/API/functionalities/thread/step_out/main.cpp
Commit 935bacd3a7244f04b7f39818e3fc589529474d13 by llvm-dev
[DAG] SimplifyDemandedBits - correctly adjust truncated shift amount type

As noticed on D56387, for vectors we must always correctly adjust the shift amount type during truncation (not just after legalization). We were getting away with it as we currently only accepted scalars via the dyn_cast<ConstantSDNode>.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit 0ca81b90d19d395c4891b7507cec0f063dd26d22 by llvm-dev
[X86][SSE] Add uitofp(trunc(and(lshr(x,c)))) vector test

Reduced from regression reported by @hans on D56387
The file was modifiedllvm/test/CodeGen/X86/uint_to_fp-3.ll
Commit 294e2544c992de82c180c080f6359db8f02005d0 by frgossen
Add log1p lowering from standard to NVVM intrinsics

Differential Revision: https://reviews.llvm.org/D95130
The file was modifiedmlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
The file was modifiedmlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
Commit 69bc0990a9181e6eb86228276d2f59435a7fae67 by llvm-dev
[DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE (REAPPLIED).

Add DemandedElts support inside the TRUNCATE analysis.

REAPPLIED - this was reverted by @hans at rGa51226057fc3 due to an issue with vector shift amount types, which was fixed in rG935bacd3a724 and an additional test case added at rG0ca81b90d19d

Differential Revision: https://reviews.llvm.org/D56387
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
The file was modifiedllvm/test/CodeGen/X86/min-legal-vector-width.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vmulh.ll
The file was modifiedllvm/test/CodeGen/ARM/lowerMUL-newload.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
The file was modifiedllvm/test/CodeGen/X86/uint_to_fp-3.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc.ll
The file was modifiedllvm/test/CodeGen/AArch64/lowerMUL-newload.ll
The file was modifiedllvm/test/CodeGen/X86/known-signbits-vector.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/X86/combine-sra.ll
The file was modifiedllvm/test/CodeGen/AArch64/aarch64-smull.ll
Commit 4ef38f9c1255dcaa3f834cf376e55f8a7bdc5810 by frgossen
Add log1p lowering from standard to ROCDL intrinsics

Differential Revision: https://reviews.llvm.org/D95129
The file was modifiedmlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
The file was modifiedmlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
Commit 2b4716d6dff1c9a5e64b3487a0b2388e3ff18b30 by mikael.holmen
[MC] Use std::make_tuple to make some toolchains happy again

My toolchain (LLVM 8.0, libstdc++ 5.4.0) complained with:

12:27:43 ../lib/MC/MCDwarf.cpp:814:10: error: chosen constructor is explicit in copy-initialization
12:27:43   return {Offset, Size, SetDelta};
12:27:43          ^~~~~~~~~~~~~~~~~~~~~~~~
12:27:43 /proj/flexasic/app/llvm/8.0/bin/../lib/gcc/x86_64-unknown-linux-gnu/5.4.0/../../../../include/c++/5.4.0/tuple:479:19: note: explicit constructor declared here
12:27:43         constexpr tuple(_UElements&&... __elements)
12:27:43                   ^
12:27:43 1 error generated.

This commit adds explicit calls to std::make_tuple to work around
the problem.
The file was modifiedllvm/lib/MC/MCDwarf.cpp
Commit 070af1b7887f80383d8473bb4da565edbde6c6b0 by spatel
[InstCombine] avoid crashing on attribute propagation

In https://llvm.org/PR48810 , we are crashing while trying to
propagate attributes from mempcpy (returns void*) to memcpy
(returns nothing - void).

We can avoid the crash by removing known incompatible
attributes for the void return type.

I'm not sure if this goes far enough (should we just drop all
attributes since this isn't the same function?). We also need
to audit other transforms in LibCallSimplifier to make sure
there are no other cases that have the same problem.

Differential Revision: https://reviews.llvm.org/D95088
The file was modifiedllvm/test/Transforms/InstCombine/mempcpy.ll
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
Commit 726de41e2bfb1d0d65e08f103dcb12810fe99d60 by 1.int32
[clang][AST] Add get functions for CXXFoldExpr paren locations.

Reviewed By: hokein

Differential Revision: https://reviews.llvm.org/D94787
The file was modifiedclang/include/clang/AST/ExprCXX.h
Commit 37510f69b4cb8d76064f108d57bebe95984a23ae by Raphael Isemann
[lldb][NFC] Fix build with GCC<6

GCC/libstdc++ before 6.1 can't handle scoped enums as unordered_map keys. LLVM
(and some build) bots officially support some GCC 5.x versions, so this patch
just makes the enum unscoped until we can require GCC 6.x.
The file was modifiedlldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h
Commit 20566a2ed825c05d56708552d33d95ee12255f46 by Matthew.Arsenault
AMDGPU: Add occupancy to serialized MachineFunctionInfo

Not sure about the default value handling, but also not sure
defaulting to a theoretically subtarget dependent value.
The file was modifiedllvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
The file was modifiedllvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h