AbortedChanges

Summary

  1. [SelectionDAG] GetDemandedBits - remove ANY_EXTEND handling (details)
  2. [PowerPC][NFC] Reclaim TSFlags bit 6 (details)
  3. Make dropTriviallyDeadConstantArrays not quadratic (details)
  4. [TargetLowering] SimplifyDemandedBits ISD::SRA multi-use handling (details)
  5. [ARM] Follow AACPS standard for volatile bit-fields access width (details)
  6. Revert "[ARM] Follow AACPS standard for volatile bit-fields access (details)
  7. [RISCV] Check the target-abi module flag matches the option (details)
  8. [clangd] Drop returntype/type when hovering over type-ish names (details)
  9. Update spelling of {analyze,insert,remove}Branch in strings and comments (details)
Commit 47f99d2ca8adbecb59d04dad550262363b513d6d by llvm-dev
[SelectionDAG] GetDemandedBits - remove ANY_EXTEND handling
Rely on SimplifyMultipleUseDemandedBits fallback instead.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit d7032bc3c009d3d2e7fdd6427fa629589fe93096 by Jinsong Ji
[PowerPC][NFC] Reclaim TSFlags bit 6
We removed UseVSXReg flag in https://reviews.llvm.org/D58685 But we did
not reclain the bit 6 it was assigned, this will become confusing and a
hole later.. We should reclaim it as early as possible before new bits.
Reviewed By: sfertile
Differential Revision: https://reviews.llvm.org/D72649
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrFormats.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.h
Commit 81f385b0c6ea37dd7195a65be162c75bbdef29d2 by benny.kra
Make dropTriviallyDeadConstantArrays not quadratic
Only look at the operands of dead constant arrays instead of all
constant arrays again.
The file was modifiedllvm/lib/IR/LLVMContextImpl.cpp
Commit f04284cf1d491a5d9a1eebfd14ed2eb6342f5e47 by llvm-dev
[TargetLowering] SimplifyDemandedBits ISD::SRA multi-use handling
Call SimplifyMultipleUseDemandedBits to peek through extended source
args with multiple uses
The file was modifiedllvm/test/CodeGen/X86/const-shift-of-constmasked.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit 6a24339a45246b66bd3de88cc9c6a5b5e77c0645 by diogo.sampaio
[ARM] Follow AACPS standard for volatile bit-fields access width
Summary: This patch resumes the work of D16586. According to the AAPCS,
volatile bit-fields should be accessed using containers of the widht of
their declarative type. In such case:
``` struct S1 {
short a : 1;
}
``` should be accessed using load and stores of the width
(sizeof(short)), where now the compiler does only load the minimum
required width (char in this case). However, as discussed in D16586,
that could overwrite non-volatile bit-fields, which conflicted with C
and C++ object models by creating data race conditions that are not part
of the bit-field, e.g.
``` struct S2 {
short a;
int  b : 16;
}
``` Accessing `S2.b` would also access `S2.a`.
The AAPCS Release 2019Q1.1
(https://static.docs.arm.com/ihi0042/g/aapcs32.pdf) section 8.1 Data
Types, page 35, "Volatile bit-fields - preserving number and width of
container accesses" has been updated to avoid conflict with the C++
Memory Model. Now it reads in the note:
``` This ABI does not place any restrictions on the access widths of
bit-fields where the container overlaps with a non-bit-field member.
This is because the C/C++ memory model defines these as being separate
memory locations, which can be accessed by two threads
simultaneously. For this reason, compilers must be permitted to use a
narrower memory access width (including splitting the access
into multiple instructions) to avoid writing to a different memory
location.
```
I've updated the patch D16586 to follow such behavior by verifying that
we only change volatile bit-field access when:
- it won't overlap with any other non-bit-field member
- we only access memory inside the bounds of the record
Regarding the number of memory accesses, that should be preserved, that
will be implemented by D67399.
Reviewers: rsmith, rjmccall, eli.friedman, ostannard
Subscribers: ostannard, kristof.beyls, cfe-commits, carwil, olista01
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72932
The file was modifiedclang/test/CodeGen/aapcs-bitfield.c
The file was modifiedclang/lib/CodeGen/CGExpr.cpp
The file was modifiedclang/lib/CodeGen/CGValue.h
The file was modifiedclang/lib/CodeGen/CodeGenFunction.h
Commit 2147703bde1e1a7a1b89ccb66f55d36fd17620f1 by diogo.sampaio
Revert "[ARM] Follow AACPS standard for volatile bit-fields access
width"
This reverts commit 6a24339a45246b66bd3de88cc9c6a5b5e77c0645. Submitted
using ide button by mistake
The file was modifiedclang/lib/CodeGen/CGValue.h
The file was modifiedclang/lib/CodeGen/CodeGenFunction.h
The file was modifiedclang/lib/CodeGen/CGExpr.cpp
The file was modifiedclang/test/CodeGen/aapcs-bitfield.c
Commit 1256d68093ac1696034e385bbb4cb6e516b66bea by zakk.chen
[RISCV] Check the target-abi module flag matches the option
Reviewers: lenary, asb
Reviewed By: lenary
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72768
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetMachine.cpp
The file was addedllvm/test/CodeGen/RISCV/module-target-abi.ll
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
The file was addedllvm/test/CodeGen/RISCV/module-target-abi2.ll
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
Commit 1fbb1d6df0113ca341f6d257bc72e07343dd861a by kadircet
[clangd] Drop returntype/type when hovering over type-ish names
Summary: Some names, e.g. constructor/destructor/conversions, already
contain the type info, no need to duplicate them in the hoverinfo.
Fixes https://github.com/clangd/clangd/issues/252
Reviewers: sammccall, ilya-biryukov
Subscribers: MaskRay, jkorous, arphaman, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D73110
The file was modifiedclang-tools-extra/clangd/unittests/HoverTests.cpp
The file was modifiedclang-tools-extra/clangd/Hover.cpp
Commit 020041d99b508ed5f207c0896a19b3e85c942ee7 by kparzysz
Update spelling of {analyze,insert,remove}Branch in strings and comments
These names have been changed from CamelCase to camelCase, but there
were many places (comments mostly) that still used the old names.
This change is NFC.
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp
The file was modifiedllvm/test/CodeGen/SystemZ/int-cmp-02.ll
The file was modifiedllvm/lib/Target/AMDGPU/R600InstrInfo.cpp
The file was modifiedllvm/lib/CodeGen/MachineBlockPlacement.cpp
The file was modifiedllvm/lib/CodeGen/BranchFolding.cpp
The file was modifiedllvm/lib/Target/XCore/XCoreInstrInfo.cpp
The file was modifiedllvm/lib/Target/Lanai/LanaiAsmPrinter.cpp
The file was modifiedllvm/lib/CodeGen/EarlyIfConversion.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
The file was modifiedllvm/test/CodeGen/SystemZ/branch-08.ll
The file was modifiedllvm/lib/CodeGen/MachineBasicBlock.cpp
The file was modifiedlibcxxabi/test/test_demangle.pass.cpp
The file was modifiedllvm/lib/Target/ARC/ARCInstrInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
The file was modifiedllvm/include/llvm/MC/MCInstrDesc.h
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/docs/WritingAnLLVMBackend.rst
The file was modifiedllvm/lib/Target/Hexagon/HexagonInstrInfo.h
The file was modifiedllvm/include/llvm/CodeGen/MachineInstr.h