Started 28 days ago
Took 8 hr 38 min

Success Build #952 (Jan 23, 2020 5:24:05 AM)

Changes
  1. [LLD] [COFF] Silence a GCC warning about an unused variable. NFC. (details)
  2. [SelectionDAG] Compute Known + Sign Bits - merge INSERT_SUBVECTOR (details)
  3. [SelectionDAG] ComputeKnownBits - merge EXTRACT_VECTOR_ELT known/unknown (details)
  4. [FileCheck] Strengthen error checks in unit tests (details)
  5. [llvm-exegesis] Don't use unsupported aliasing instructions (details)
  6. [ARM,MVE] Revise immediate VBIC/VORR to look more like NEON. (details)
  7. [ARM,MVE] Support immediate vbicq,vorrq,vmvnq intrinsics. (details)
  8. [AArch64][SVE] Add first-faulting load intrinsic (details)
  9. Treat C# `using` as a control statement (details)
  10. [Alignement][NFC] Deprecate untyped CreateAlignedLoad (details)
  11. [LoopRotate] add ability to repeat loop rotation until non-deoptimizing (details)
  12. [SelectionDAG] Compute Known + Sign Bits - merge INSERT_VECTOR_ELT (details)
  13. [NFC][RDA] Make the interface const (details)
  14. [gn build] Port 2f6987ba61c (details)
  15. [CodeGen] Make use of MachineInstrBuilder::getReg (details)
  16. Revert "[mlir] Add baseAttr to TypedArrayAttrBase." (details)
  17. [tablegen] Emit string literals instead of char arrays (details)
  18. [ARM,MVE] Make the MVE intrinsics work in C++! (details)
  19. [VE][NFC] re-write RR* isel class using null_frag (details)
  20. [clang][CodeComplete] Make completion work after initializer lists (details)
  21. Revert "Resubmit: [JumpThreading] Thread jumps through two basic blocks" (details)
  22. [VE] add, sub, left/right shift isel patterns (details)
  23. [Dsymutil][Debuginfo][NFC] #4 Refactor dsymutil to separate DWARF (details)
  24. Revert "[tablegen] Emit string literals instead of char arrays" (details)
  25. [Hexagon] Remove unused operand definitions: s10_0Imm and s10_6Imm (details)
  26. Fix GCC warning/error '-fpermission'. NFC. (details)
  27. [hip] Remove `-Werror=format-nonliteral` (details)
  28. [OPENMP]Fix use of local allocators in allocate clauses. (details)
  29. [OpenMP] change omp_atk_* and omp_atv_* enumerators to lowercase [NFC] (details)
  30. [X86][AVX] Add AVX1/AVX2 ashr vector tests (details)
  31. [SelectionDAG] ComputeNumSignBits - add ISD::SUB demanded elts support (details)
  32. [NFC][ARM] Add test (details)
  33. AMDGPU: Check for other uses when looking through casted select (details)
  34. [Alignment][NFC] Use Align with CreateAlignedStore (details)
  35. [X86][SSE] Add ComputeNumSignBits tests for (ADD (AND X, 1), -1) vectors (details)
  36. [SelectionDAG] ComputeNumSignBits - add ISD::ADD vector support (details)
  37. clang-cl: Parse /QIntel-jcc-erratum (details)
  38. GlobalISel: Use Register (details)
  39. AMDGPU/GlobalISel: Select V_ADD3_U32/V_XOR3_B32 (details)
  40. [RDA] Skip debug values (details)

Started by upstream project LLDB Incremental build number 6522
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This run spent:

  • 10 hr waiting;
  • 8 hr 38 min build duration;
  • 15 hr total from scheduled to completion.
Revision: a286f239d9544e995d8436a57199d4923306a7ca
  • refs/remotes/origin/master
Revision: 05532575e88a45774dcf470d4639a01a4e501f66
  • refs/remotes/origin/master
Revision: a286f239d9544e995d8436a57199d4923306a7ca
  • refs/remotes/origin/master
Test Result (no failures)
    Revision: 6a075b6de4cafebec9ca1ff9eec7229a617c93f6
    • llvmorg-5.0.2
    Revision: d0d8eb2e5415b8be29343e3c17a18e49e67b5551
    • llvmorg-7.0.1
    Revision: 0399d5a9682b3cef71c653373e38890c63c4c365
    • llvmorg-9.0.0