SuccessChanges

Summary

  1. [LLD] [COFF] Silence a GCC warning about an unused variable. NFC. (details)
  2. [SelectionDAG] Compute Known + Sign Bits - merge INSERT_SUBVECTOR (details)
  3. [SelectionDAG] ComputeKnownBits - merge EXTRACT_VECTOR_ELT known/unknown (details)
  4. [FileCheck] Strengthen error checks in unit tests (details)
  5. [llvm-exegesis] Don't use unsupported aliasing instructions (details)
  6. [ARM,MVE] Revise immediate VBIC/VORR to look more like NEON. (details)
  7. [ARM,MVE] Support immediate vbicq,vorrq,vmvnq intrinsics. (details)
  8. [AArch64][SVE] Add first-faulting load intrinsic (details)
  9. Treat C# `using` as a control statement (details)
  10. [Alignement][NFC] Deprecate untyped CreateAlignedLoad (details)
  11. [LoopRotate] add ability to repeat loop rotation until non-deoptimizing (details)
  12. [SelectionDAG] Compute Known + Sign Bits - merge INSERT_VECTOR_ELT (details)
  13. [NFC][RDA] Make the interface const (details)
  14. [gn build] Port 2f6987ba61c (details)
  15. [CodeGen] Make use of MachineInstrBuilder::getReg (details)
  16. Revert "[mlir] Add baseAttr to TypedArrayAttrBase." (details)
  17. [tablegen] Emit string literals instead of char arrays (details)
  18. [ARM,MVE] Make the MVE intrinsics work in C++! (details)
  19. [VE][NFC] re-write RR* isel class using null_frag (details)
  20. [clang][CodeComplete] Make completion work after initializer lists (details)
  21. Revert "Resubmit: [JumpThreading] Thread jumps through two basic blocks" (details)
  22. [VE] add, sub, left/right shift isel patterns (details)
  23. [Dsymutil][Debuginfo][NFC] #4 Refactor dsymutil to separate DWARF (details)
  24. Revert "[tablegen] Emit string literals instead of char arrays" (details)
  25. [Hexagon] Remove unused operand definitions: s10_0Imm and s10_6Imm (details)
  26. Fix GCC warning/error '-fpermission'. NFC. (details)
  27. [hip] Remove `-Werror=format-nonliteral` (details)
  28. [OPENMP]Fix use of local allocators in allocate clauses. (details)
  29. [OpenMP] change omp_atk_* and omp_atv_* enumerators to lowercase [NFC] (details)
  30. [X86][AVX] Add AVX1/AVX2 ashr vector tests (details)
  31. [SelectionDAG] ComputeNumSignBits - add ISD::SUB demanded elts support (details)
  32. [NFC][ARM] Add test (details)
  33. AMDGPU: Check for other uses when looking through casted select (details)
  34. [Alignment][NFC] Use Align with CreateAlignedStore (details)
  35. [X86][SSE] Add ComputeNumSignBits tests for (ADD (AND X, 1), -1) vectors (details)
  36. [SelectionDAG] ComputeNumSignBits - add ISD::ADD vector support (details)
  37. clang-cl: Parse /QIntel-jcc-erratum (details)
  38. GlobalISel: Use Register (details)
  39. AMDGPU/GlobalISel: Select V_ADD3_U32/V_XOR3_B32 (details)
  40. [RDA] Skip debug values (details)
Commit e6b0ce70bdd888f4c1863941db8928040bbc2eff by martin
[LLD] [COFF] Silence a GCC warning about an unused variable. NFC.
The file was modifiedlld/COFF/Driver.cpp
Commit 98da49d979198366d4710ac65a3786b9a8f3b4c1 by llvm-dev
[SelectionDAG] Compute Known + Sign Bits - merge INSERT_SUBVECTOR
known/unknown index paths
Match the approach in SimplifyDemandedBits where we calculate the
demanded elts and then have a common path for the
ComputeKnownBits/ComputeNumSignBits call, additionally we only ever need
original demanded elts of the base vector even if the index is unknown.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit 03cae086f41c48a971329dc5a1f4a76c1c6af036 by llvm-dev
[SelectionDAG] ComputeKnownBits - merge EXTRACT_VECTOR_ELT known/unknown
index paths
Match the approach in SimplifyDemandedBits/ComputeNumSignBits where we
calculate the demanded elts and then have a common path for the
ComputeKnownBits call.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit f1ad192915f64e3eeedfb01aa1073e81bff4e1a1 by thomasp
[FileCheck] Strengthen error checks in unit tests
Summary: This commit adds error checking beyond UndefVarError and fix a
number of Error/Expected related idioms:
- use (EXPECT|ASSERT)_THAT_(ERROR|EXPECTED) instead of errorToBool or
boolean operator
- ASSERT when a further check require the check to be successful to give
a correct result
Reviewers: jhenderson, jdenny, probinson, grimar, arichardson, rnk
Reviewed By: jhenderson
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72914
The file was modifiedllvm/unittests/Support/FileCheckTest.cpp
Commit e8fc8507dacbab119a1ca14535d7c75f0514a078 by Milos.Stojanovic
[llvm-exegesis] Don't use unsupported aliasing instructions
Since some instruction types aren't allowed as the main instruction also
don't allow them for aliasing instructions.
Differential Revision: https://reviews.llvm.org/D73220
The file was modifiedllvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp
Commit 772e4931932270a82f38c83d4344c800b2f54eff by simon.tatham
[ARM,MVE] Revise immediate VBIC/VORR to look more like NEON.
Summary: In NEON, the immediate forms of VBIC and VORR are each
represented as a single MC instruction, which takes its immediate
operand already encoded in a NEON-friendly format: 8 data bits, plus
some control bits indicating how to expand them into a full vector.
In MVE, we represented immediate VBIC and VORR as four separate MC
instructions each, for an 8-bit immediate shifted left by 0, 8, 16 or 24
bits. For each one, the value of the immediate operand is in the
'natural' form, i.e. the numerical value that would actually be BICed or
ORRed into each vector lane (and also the same value shown in assembly).
For example, MVE_VBICIZ16v4i32 takes an operand such as 0xab0000, which
NEON would represent as 0xab | (control bits << 8).
The MVE approach is superficially nice (it makes assembly input and
output easy, and it's also nice if you're manually constructing
immediate VBICs). But it turns out that it's better for isel if we make
the NEON and MVE instructions work the same, because the ARMISD::VBICIMM
and VORRIMM node types already encode their immediate into the NEON
format, so it's easier if we can just use it.
Also, this commit reduces the total amount of code rather than
increasing it, which is surely an indication that it really is simpler
to do it this way!
Reviewers: dmgreen, ostannard, miyuki, MarkMurrayARM
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73205
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
The file was modifiedllvm/unittests/Target/ARM/MachineInstrTest.cpp
The file was modifiedllvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was modifiedllvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
Commit 4321c6af28e9cc26d385fc388b8f0a74b32741c1 by simon.tatham
[ARM,MVE] Support immediate vbicq,vorrq,vmvnq intrinsics.
Summary: Immediate vmvnq is code-generated as a simple vector constant
in IR, and left to the backend to recognize that it can be created with
an MVE VMVN instruction. The predicated version is represented as a
select between the input and the same constant, and I've added a
Tablegen isel rule to turn that into a predicated VMVN. (That should be
better than the previous VMVN + VPSEL: it's the same number of
instructions but now it can fold into an adjacent VPT block.)
The unpredicated forms of VBIC and VORR are done by enabling the same
isel lowering as for NEON, recognizing appropriate immediates and
rewriting them as ARMISD::VBICIMM / ARMISD::VORRIMM SDNodes, which I
then instruction-select into the right MVE instructions (now that I've
also reworked those instructions to use the same MC operand encoding).
In order to do that, I had to promote the Tablegen SDNode instance
`NEONvorrImm` to a general `ARMvorrImm` available in MVE as well, and
similarly for `NEONvbicImm`.
The predicated forms of VBIC and VORR are represented as a vector select
between the original input vector and the output of the unpredicated
operation. The main convenience of this is that it still lets me use the
existing isel lowering for VBICIMM/VORRIMM, and not have to write
another copy of the operand encoding translation code.
This intrinsic family is the first to use the `imm_simd` system I put
into the MveEmitter tablegen backend. So, naturally, it showed up a bug
or two (emitting bogus range checks and the like). Fixed those, and
added a full set of tests for the permissible immediates in the existing
Sema test.
Also adjusted the isel pattern for `vmovlb.u8`, which stopped matching
because lowering started turning its input into a VBICIMM. Now it
recognizes the VBICIMM instead.
Reviewers: dmgreen, MarkMurrayARM, miyuki, ostannard
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D72934
The file was addedclang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
The file was modifiedllvm/lib/Target/ARM/ARMInstrNEON.td
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMInstrInfo.td
The file was addedllvm/test/CodeGen/Thumb2/mve-intrinsics/bitwise-imm.ll
The file was modifiedclang/include/clang/Basic/arm_mve.td
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/include/clang/Basic/arm_mve_defs.td
The file was modifiedclang/test/Sema/arm-mve-immediates.c
The file was modifiedclang/utils/TableGen/MveEmitter.cpp
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
Commit aa0f37e14a877bf5bb7c28506b94a8a0ea6d4791 by kerry.mclaughlin
[AArch64][SVE] Add first-faulting load intrinsic
Summary: Implements the llvm.aarch64.sve.ldff1 intrinsic and DAG combine
rules for first-faulting loads with sign & zero extends
Reviewers: sdesmalen, efriedma, andwar, dancgr, rengolin
Reviewed By: sdesmalen
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl,
cameron.mcinally, cfe-commits, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73025
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was addedllvm/test/CodeGen/AArch64/sve-intrinsics-loads-ff.ll
Commit 1e0174a93cfd364bffd12abc8f0148509d0d0f75 by krasimir
Treat C# `using` as a control statement
Contributed by jbcoe!
Summary: Unless SpaceBeforeParensOptions is set to SBPO_Never, a space
will be put between `using` and `(` in C# code.
Reviewers: klimek, MyDeveloperDay, krasimir
Reviewed By: krasimir
Subscribers: MyDeveloperDay, cfe-commits
Tags: #clang-format, #clang
Differential Revision: https://reviews.llvm.org/D72144
The file was modifiedclang/lib/Format/TokenAnnotator.cpp
The file was modifiedclang/unittests/Format/FormatTestCSharp.cpp
Commit 279fa8e0064e3d0bd1646b8efdb94045585dd924 by gchatelet
[Alignement][NFC] Deprecate untyped CreateAlignedLoad
Summary: This is patch is part of a series to introduce an Alignment
type. See this thread for context:
http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this
patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: arsenm, jvesely, nhaehnle, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73260
The file was modifiedllvm/include/llvm/IR/IRBuilder.h
The file was modifiedllvm/include/llvm/IR/Instructions.h
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
The file was modifiedllvm/lib/Transforms/Scalar/Scalarizer.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
The file was modifiedllvm/lib/Transforms/Scalar/SROA.cpp
The file was modifiedllvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
The file was modifiedllvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/ScalarizeMaskedMemIntrin.cpp
The file was modifiedllvm/lib/Target/X86/X86InterleavedAccess.cpp
The file was modifiedllvm/lib/CodeGen/AtomicExpandPass.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
The file was modifiedllvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
The file was modifiedllvm/lib/IR/AutoUpgrade.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/lib/Target/ARM/ARMParallelDSP.cpp
Commit 2f6987ba61cc31c16c64f511e5cbc76b52dc67b3 by fedor.sergeev
[LoopRotate] add ability to repeat loop rotation until non-deoptimizing
exit is found
In case of loops with multiple exit where all-but-one exit are
deoptimizing it might happen that the first rotation will end up with
latch having a deoptimizing exit. This makes the loop unsuitable for
trip-count analysis (say, getLoopEstimatedTripCount) as well as for loop
transformations that know how to handle multple deoptimizing exits.
It pretty much means that canonical form in multple-deoptimizing-exits
case should be with non-deoptimizing exit at latch. Teach loop-rotation
to reach this canonical form by repeating rotation.
-loop-rotate-multi option introduced to control this behavior, currently
disabled by default.
Reviewers: skatkov, asbirlea, reames, fhahn Reviewed By: skatkov
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73058
The file was modifiedllvm/unittests/Transforms/Utils/CMakeLists.txt
The file was addedllvm/unittests/Transforms/Utils/LoopRotationUtilsTest.cpp
The file was addedllvm/test/Transforms/LoopRotate/multiple-deopt-exits.ll
The file was modifiedllvm/lib/Transforms/Utils/LoopRotationUtils.cpp
Commit 48d4ba8fb2954d58d24f1ffe9f38045c537cf7b3 by llvm-dev
[SelectionDAG] Compute Known + Sign Bits - merge INSERT_VECTOR_ELT
known/unknown index paths
Match the approach in SimplifyDemandedBits where we calculate the
demanded elts and then have a common path for the
ComputeKnownBits/ComputeNumSignBits call.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit 0d1468db58535900270a3d3d10ed61d7d45dc4b9 by sam.parker
[NFC][RDA] Make the interface const
Make all the public query methods const.
The file was modifiedllvm/include/llvm/CodeGen/ReachingDefAnalysis.h
The file was modifiedllvm/lib/CodeGen/ReachingDefAnalysis.cpp
Commit d6a97b049f754f899112dc7b43a746269f7d3026 by llvmgnsyncbot
[gn build] Port 2f6987ba61c
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/Transforms/Utils/BUILD.gn
Commit b482e1bfe29d135dc974bb21b87f95e95dfd605a by jay.foad
[CodeGen] Make use of MachineInstrBuilder::getReg
Reviewers: arsenm
Subscribers: wdng, hiraditya, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73262
The file was modifiedllvm/lib/CodeGen/MachineSSAUpdater.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64CallLowering.cpp
The file was modifiedllvm/unittests/CodeGen/GlobalISel/CSETest.cpp
The file was modifiedllvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMInstructionSelector.cpp
The file was modifiedllvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.cpp
The file was modifiedllvm/unittests/CodeGen/GlobalISel/ConstantFoldingTest.cpp
The file was modifiedllvm/lib/Target/X86/X86CallLowering.cpp
Commit c8695ba9cdebfc25af3312a84d91ae6f0f98487b by zinenko
Revert "[mlir] Add baseAttr to TypedArrayAttrBase."
This reverts commit eec36909c18b8788773abc95d199e6acde6eb42c.
This modeling is incorrect. baseAttr is intended for attribute
decorators that are not backed by C++ attribute classes. It essentially
says DerivedAttr isa BaseAttr, which is wrong for ArrayAttr classes. If
one needs to store the element type, it should be stored as a separate
filed in the tablegen class.
The file was modifiedmlir/include/mlir/IR/OpBase.td
Commit ce23515f5ab01161c98449d833b3ae013b553aa8 by luke.drummond
[tablegen] Emit string literals instead of char arrays
This changes the generated (Instr|Asm|Reg|Regclass)Name tables from this
form:
   extern const char HexagonInstrNameData[] = {
     /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0,
     /* 9 */ 'E', 'N', 'D', 'L', 'O', 'O', 'P', '0', 0,
     /* 18 */ 'V', '6', '_', 'v', 'd', 'd', '0', 0,
     /* 26 */ 'P', 'S', '_', 'v', 'd', 'd', '0', 0,
     [...]
   };
...to this:
    extern const char HexagonInstrNameData[] = {
     /* 0 */ "G_FLOG10\0"
     /* 9 */ "ENDLOOP0\0"
     /* 18 */ "V6_vdd0\0"
     /* 26 */ "PS_vdd0\0"
     [...]
   };
This should make debugging and exploration a lot easier for mortals,
while providing a significant compile-time reduction for common
compilers.
To avoid issues with low implementation limits, this is disabled by
default for visual studio or when cross-compiling.
To force output one way or the other, pass
`--long-string-literals=<bool>` to `tablegen`
Reviewers: mstorsjo, rnk
Subscribers: llvm-commit
Differential Revision: https://reviews.llvm.org/D73044
The file was modifiedllvm/utils/TableGen/InstrInfoEmitter.cpp
The file was modifiedllvm/cmake/modules/TableGen.cmake
The file was modifiedllvm/utils/TableGen/TableGen.cpp
The file was modifiedllvm/utils/TableGen/AsmWriterEmitter.cpp
The file was modifiedllvm/utils/TableGen/SequenceToOffsetTable.h
The file was modifiedllvm/utils/TableGen/RegisterInfoEmitter.cpp
Commit 98ea4b30c2c4e122defce039e29f7023aa2663e7 by simon.tatham
[ARM,MVE] Make the MVE intrinsics work in C++!
Summary: Apparently nobody has tried this in months of development. It
turns out that `FunctionDecl::getBuiltinID` will never consider a
function to be a builtin if it is in C++ and not extern "C". So none of
the function declarations in <arm_mve.h> are recognized as builtins when
clang is compiling in C++ mode: it just emits calls to them as ordinary
functions, which then turn out not to exist at link time.
The trivial fix is to wrap most of arm_mve.h in an extern "C".
Added a test in clang/test/CodeGen/arm-mve-intrinsics which checks basic
functioning of the MVE header file in C++ mode. I've filled it with
copies of existing test functions from other files in that directory,
including a few moderately tricky cases of overloading (in particular
one that relies on the strict-polymorphism attribute added in D72518).
(I considered making //every// test in that directory compile in both C
and C++ mode and check the code generation was identical. But I think
that would increase testing time by more than the value it adds, and
also update_cc_test_checks gets confused when the output function name
varies between RUN lines.)
Reviewers: LukeGeeson, MarkMurrayARM, miyuki, dmgreen
Reviewed By: MarkMurrayARM
Subscribers: kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D73268
The file was modifiedclang/utils/TableGen/MveEmitter.cpp
The file was addedclang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
Commit 9187073f3e051903b4c1f86e5fce0e1c819a1c34 by simon.moll
[VE][NFC] re-write RR* isel class using null_frag
Summary: Re-write RR* using null_frag to avoid duplication in upcoming
patches.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D73259
The file was modifiedllvm/lib/Target/VE/VEInstrInfo.td
Commit 24364cd12bbfa2e58fa74bfb49d4ea85c64c0951 by kadircet
[clang][CodeComplete] Make completion work after initializer lists
Summary: CodeCompletion was not being triggered after successfully
parsed initializer lists, e.g.
```cpp void foo(int, bool); void bar() {
foo({1}^, false);
}
```
CodeCompletion would suggest the function foo as an overload candidate
up until the point marked with `^` but after that point we do not
trigger signature help since parsing succeeds.
This patch handles that case by failing in parsing expression lists
whenever we see a codecompletion token, in addition to getting an
invalid subexpression.
Reviewers: sammccall
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D73177
The file was modifiedclang/test/CodeCompletion/call.cpp
The file was modifiedclang/lib/Parse/ParseExpr.cpp
Commit 41784bed01543315a1d03141e6ddc023fd914c0b by kazu
Revert "Resubmit: [JumpThreading] Thread jumps through two basic blocks"
This reverts commit 53b68e676faf208b4a8f817e9bd4ddd522cc6006.
Our internal tests are showing breakage with this patch.
The file was removedllvm/test/Transforms/JumpThreading/thread-two-bbs1.ll
The file was modifiedllvm/include/llvm/Transforms/Scalar/JumpThreading.h
The file was removedllvm/test/Transforms/JumpThreading/thread-two-bbs2.ll
The file was removedllvm/test/Transforms/JumpThreading/thread-two-bbs3.ll
The file was modifiedllvm/lib/Transforms/Scalar/JumpThreading.cpp
Commit 784204fd7edd56ebfe6f7aafc68f56a0692613be by simon.moll
[VE] add, sub, left/right shift isel patterns
Summary: Add, sub, left/right shift isel patterns and tests for i32/i64
and fp32/fp64.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D73207
The file was addedllvm/test/CodeGen/VE/right_shift.ll
The file was addedllvm/test/CodeGen/VE/subtraction.ll
The file was modifiedllvm/lib/Target/VE/VEInstrInfo.td
The file was addedllvm/test/CodeGen/VE/addition.ll
The file was addedllvm/test/CodeGen/VE/left_shift.ll
Commit a8c5a461a8e81684d28ca06eb2f65bf43a88e03b by a.v.lapshin
[Dsymutil][Debuginfo][NFC] #4 Refactor dsymutil to separate DWARF
optimizing part.
Summary: The primary goal of this refactoring is to separate DWARF
optimizing part. So that it could be reused by linker or by any other
client. There was a thread on llvm-dev discussing the necessity of such
a refactoring:
http://lists.llvm.org/pipermail/llvm-dev/2019-September/135068.html.
This is a final part from series of patches for dsymutil. Previous
patches : D71068, D71839, D72476. This patch:
1. Creates lib/DWARFLinker interface :
   void addObjectFile(DwarfLinkerObjFile &ObjFile);
  bool link();
  void setOptions;
1. Moves all linking logic from tools/dsymutil/DwarfLinkerForBinary
  into lib/DWARFLinker. 2. Renames RelocationManager into
AddressesManager. 3. Remarks creation logic moved from separate parallel
execution
  into object file loading routine.
Testing: it passes "check-all" lit testing. MD5 checksum for clang .dSYM
bundle matches for the dsymutil with/without that patch.
Reviewers: JDevlieghere, friss, dblaikie, aprantl, jdoerfert
Reviewed By: JDevlieghere
Subscribers: merge_guards_bot, hiraditya, jfb, llvm-commits, probinson,
thegameg
Tags: #llvm, #debug-info
Differential Revision: https://reviews.llvm.org/D72915
The file was modifiedllvm/tools/dsymutil/LinkUtils.h
The file was modifiedllvm/tools/dsymutil/DwarfLinkerForBinary.cpp
The file was modifiedllvm/include/llvm/CodeGen/DIE.h
The file was modifiedllvm/lib/DWARFLinker/DWARFLinker.cpp
The file was modifiedllvm/tools/dsymutil/DwarfStreamer.cpp
The file was modifiedllvm/tools/dsymutil/DwarfLinkerForBinary.h
The file was modifiedllvm/include/llvm/DWARFLinker/DWARFLinker.h
Commit e464b31c1565204e3be114d043bcbf4de61fe2e9 by jaskiewiczs
Revert "[tablegen] Emit string literals instead of char arrays"
This reverts commit ce23515f5ab01161c98449d833b3ae013b553aa8.
That commit broke some builds on Windows:
http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/13870
The file was modifiedllvm/cmake/modules/TableGen.cmake
The file was modifiedllvm/utils/TableGen/AsmWriterEmitter.cpp
The file was modifiedllvm/utils/TableGen/RegisterInfoEmitter.cpp
The file was modifiedllvm/utils/TableGen/SequenceToOffsetTable.h
The file was modifiedllvm/utils/TableGen/InstrInfoEmitter.cpp
The file was modifiedllvm/utils/TableGen/TableGen.cpp
Commit cc4b716a379fab76dca734716730767d7de8d557 by kparzysz
[Hexagon] Remove unused operand definitions: s10_0Imm and s10_6Imm
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepOperands.td
The file was modifiedllvm/lib/Target/Hexagon/HexagonDepDecoders.inc
Commit 398175e5c718ab2a92eded571f669f3b6e036e75 by michael.hliao
Fix GCC warning/error '-fpermission'. NFC.
The file was modifiedllvm/lib/DWARFLinker/DWARFLinker.cpp
The file was modifiedllvm/include/llvm/DWARFLinker/DWARFLinker.h
Commit 49f7bc9e1e50eb8f6e065f97585b3bf0bcc23d5c by michael.hliao
[hip] Remove `-Werror=format-nonliteral`
Summary:
- It won't distinguish host and device code and trigger compilation
failure on irrelevant code.
Reviewers: sameerds, yaxunl
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D73224
The file was modifiedclang/lib/Driver/ToolChains/HIP.cpp
The file was modifiedclang/test/Driver/hip-printf.hip
Commit f3c508fe91606c7383c812838b07ed5433a00dcf by a.bataev
[OPENMP]Fix use of local allocators in allocate clauses.
If local allocator was declared and used in the allocate clause, it was
not captured in inner region. It leads to a compiler crash, need to
capture the allocator declarator.
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
The file was modifiedclang/test/OpenMP/parallel_master_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_ast_print.cpp
Commit ad24cf2a942068e5bcdda3fbe58c084715266cf3 by kkwli0
[OpenMP] change omp_atk_* and omp_atv_* enumerators to lowercase [NFC]
The OpenMP spec defines the OMP_ATK_* and OMP_ATV_* to be lowercase.
Differential Revision: https://reviews.llvm.org/D73248
The file was modifiedopenmp/runtime/src/kmp.h
The file was modifiedopenmp/runtime/test/api/omp_alloc_null_fb.c
The file was modifiedopenmp/runtime/src/kmp_alloc.cpp
The file was modifiedopenmp/runtime/src/include/omp.h.var
The file was modifiedopenmp/runtime/test/api/omp_alloc_def_fb.c
The file was modifiedopenmp/runtime/test/api/omp_alloc_hbw.c
Commit c1cac20827684949d381ae418f1868a76eaeda67 by llvm-dev
[X86][AVX] Add AVX1/AVX2 ashr vector tests
The file was modifiedllvm/test/CodeGen/X86/sar_fold64.ll
Commit fc5bbbf328bc2ef582cf1cf9ba5ac2ddfc12ea31 by llvm-dev
[SelectionDAG] ComputeNumSignBits - add ISD::SUB demanded elts support
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/X86/sar_fold64.ll
Commit 0c943c611774b6785bc9a245bf432ae75357358c by sam.parker
[NFC][ARM] Add test
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
Commit dfec702290e4cbd2fb965096788225ef3aac0986 by arsenm2
AMDGPU: Check for other uses when looking through casted select
Fixes mesa regression on ext_transform_feedback-max-varyings
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
Commit 59f95222d4c5e997342b0514984823a99a16d44b by gchatelet
[Alignment][NFC] Use Align with CreateAlignedStore
Summary: This is patch is part of a series to introduce an Alignment
type. See this thread for context:
http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this
patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet, bollu
Subscribers: arsenm, jvesely, nhaehnle, hiraditya, kerbowa, cfe-commits,
llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D73274
The file was modifiedclang/lib/CodeGen/CGObjCGNU.cpp
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp
The file was modifiedpolly/lib/CodeGen/LoopGeneratorsKMP.cpp
The file was modifiedllvm/include/llvm/IR/IRBuilder.h
The file was modifiedllvm/lib/CodeGen/ScalarizeMaskedMemIntrin.cpp
The file was modifiedpolly/lib/CodeGen/BlockGenerators.cpp
The file was modifiedllvm/lib/Target/X86/X86InterleavedAccess.cpp
The file was modifiedpolly/lib/CodeGen/RuntimeDebugBuilder.cpp
The file was modifiedllvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
The file was modifiedllvm/lib/Transforms/Scalar/Scalarizer.cpp
The file was modifiedllvm/include/llvm/IR/GlobalObject.h
The file was modifiedclang/lib/CodeGen/CGGPUBuiltin.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedllvm/lib/IR/AutoUpgrade.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
The file was modifiedclang/lib/CodeGen/CGBuilder.h
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/lib/IR/DataLayout.cpp
The file was modifiedllvm/lib/Transforms/Scalar/SROA.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp
The file was modifiedclang/lib/CodeGen/CGBlocks.cpp
The file was modifiedllvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
The file was modifiedllvm/include/llvm/IR/DataLayout.h
The file was modifiedllvm/lib/Transforms/IPO/LowerTypeTests.cpp
The file was modifiedllvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
Commit d1de6dc17cdd37f84e92da5a456099eab0cc1467 by llvm-dev
[X86][SSE] Add ComputeNumSignBits tests for (ADD (AND X, 1), -1) vectors
The file was modifiedllvm/test/CodeGen/X86/sar_fold64.ll
Commit 0fec8acdd82a69fc5419b4a9db3c92a86634729d by llvm-dev
[SelectionDAG] ComputeNumSignBits - add ISD::ADD vector support
Add missing handling for (ADD (AND X, 1), -1) uniform vectors
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/X86/sar_fold64.ll
Commit e256a775ebfcda5fd5f4d05fe40f6bb029e88f29 by hans
clang-cl: Parse /QIntel-jcc-erratum
It appears to be a new flag, see
https://github.com/MicrosoftDocs/cpp-docs/commit/c7ac1c2635a631c61d3bed9f12b31dee6d6716fe
The file was modifiedclang/test/Driver/cl-options.c
The file was modifiedclang/include/clang/Driver/CLCompatOptions.td
Commit 4faf71a14338420afc09eec261d5295439ae956a by arsenm2
GlobalISel: Use Register
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
Commit 618fa77ae4dd8244e468fce0bf144fa329f41e5b by arsenm2
AMDGPU/GlobalISel: Select V_ADD3_U32/V_XOR3_B32
The other 3-op patterns should also be theoretically handled, but
currently there's a bug in the inferred pattern complexity.
I'm not sure what the error handling strategy should be for potential
constant bus violations. I think the correct strategy is to never
produce mixed SGPR and VGPR operands in a typical VOP instruction, which
will trivially avoid them. However, it's possible to still have hand
written MIR (or erroneously transformed code) with these operands. When
these fold, the restriction will be violated. We currently don't have
any verifiers for reg bank legality. For now, just ignore the
restriction.
It might be worth triggering a DAG fallback on verifier error.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.xfail.mir
Commit 05532575e88a45774dcf470d4639a01a4e501f66 by sam.parker
[RDA] Skip debug values
Skip debug instructions when iterating through a block to find uses.
Differential Revision: https://reviews.llvm.org/D73273
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
The file was modifiedllvm/lib/CodeGen/ReachingDefAnalysis.cpp