FailedChanges

Summary

  1. [clang][ARM] Add name-mangling test for direct __fp16 arguments. (details)
  2. [InstCombine] add tests for xor-of-ors; NFC (details)
  3. [InstCombine] reduce xor-of-or's bitwise logic (PR46955) (details)
  4. AMDGPU/GlobalISel: Fix selecting broken copies for s32->s64 anyext (details)
  5. [X86][SSE] Start shuffle combining from ANY_EXTEND_VECTOR_INREG on SSE targets (details)
  6. AMDGPU/GlobalISel: Apply load bitcast to s.buffer.load intrinsic (details)
  7. Revert "[InstCombine] reduce xor-of-or's bitwise logic (PR46955)" (details)
  8. GlobalISel: Reimplement moreElementsVectorDst (details)
  9. AMDGPU/GlobalISel: Remove old hacks for boolean selection (details)
  10. GlobalISel: Handle arbitrary FewerElementsVector for G_IMPLICIT_DEF (details)
  11. [mlir] First-party modeling of LLVM types (details)
  12. [DWARFYAML] Offsets should be omitted when the OffsetEntryCount is 0. (details)
  13. [InstCombine] reduce xor-of-or's bitwise logic (PR46955); 2nd try (details)
Commit ed0e4c70c99d3afd87fb202ab03bda40512677e7 by simon.tatham
[clang][ARM] Add name-mangling test for direct __fp16 arguments.

`clang/test/CodeGenCXX/fp16-mangle.cpp` tests pointers to __fp16, but
if you give the `-fallow-half-arguments-and-returns` option, then
clang can also leave an __fp16 unmodified as a function argument or
return type. This regression test checks the name-mangling of that.

Reviewed By: miyuki

Differential Revision: https://reviews.llvm.org/D85010
The file was addedclang/test/CodeGenCXX/fp16-mangle-arg-return.cpp
Commit b57ea8ef2a8a07ffd2c05389da3f759caaa49f3e by spatel
[InstCombine] add tests for xor-of-ors; NFC
The file was modifiedllvm/test/Transforms/InstCombine/xor.ll
Commit 2265d01f2a5bd153959701e22f5be2a40e1674a3 by spatel
[InstCombine] reduce xor-of-or's bitwise logic (PR46955)

I tried to use m_Deferred() on this, but didn't find
a clean way to do that.

http://bugs.llvm.org/PR46955

https://alive2.llvm.org/ce/z/2h6QTq
The file was modifiedllvm/test/Transforms/InstCombine/xor.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit d8ef1d1251e3c0e11894ed82904dbab5e41c5711 by Matthew.Arsenault
AMDGPU/GlobalISel: Fix selecting broken copies for s32->s64 anyext

These should probably not be legal in the first place, but that might
also be a pain.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit 99a971cadff7832a846394462c39a74aac64325d by llvm-dev
[X86][SSE] Start shuffle combining from ANY_EXTEND_VECTOR_INREG on SSE targets

We already do this on AVX (+ for ZERO_EXTEND_VECTOR_INREG), but this enables it for all SSE targets - we attempted something similar back at rL357057 but hit issues with the ZERO_EXTEND_VECTOR_INREG handling (PR41249).

I'm still looking at the vector-mul.ll regression - which is due to 32-bit targets performing the load as a f64, resulting in the shuffle combiner thinking it has to create a shuffle in the float domain.
The file was modifiedllvm/test/CodeGen/X86/combine-pmuldq.ll
The file was modifiedllvm/test/CodeGen/X86/vector-reduce-mul.ll
The file was modifiedllvm/test/CodeGen/X86/mulvi32.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-math.ll
The file was modifiedllvm/test/CodeGen/X86/pmul.ll
The file was modifiedllvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-mul.ll
The file was modifiedllvm/test/CodeGen/X86/promote-cmp.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit fd63e46941fc48d4cc777ef94e185637898d0adb by Matthew.Arsenault
AMDGPU/GlobalISel: Apply load bitcast to s.buffer.load intrinsic

Should also apply this to the non-scalar buffer loads.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
Commit f19a9be385ef782140d1e551e03553daa79d1bc1 by spatel
Revert "[InstCombine] reduce xor-of-or's bitwise logic (PR46955)"

This reverts commit 2265d01f2a5bd153959701e22f5be2a40e1674a3.
Seeing bot failures after this change like:
http://lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/42586
The file was modifiedllvm/test/Transforms/InstCombine/xor.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit 1782fbbc69482e76eee8af203694bb771a44c921 by Matthew.Arsenault
GlobalISel: Reimplement moreElementsVectorDst

Use pad with undef and unmerge with unused results. This is annoyingly
similar to several other places in LegalizerHelper, but they're all
slightly different.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
The file was modifiedllvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
Commit 2414bab5d7d6b5b247f3f3b97140a2673fa8414b by Matthew.Arsenault
AMDGPU/GlobalISel: Remove old hacks for boolean selection

There were various hacks used to try to avoid making s1 SGPR vs. s1
VCC ambiguous after constraining the register before we had a strategy
to deal with this. This also attempted to handle undef operands, which
are now illegal gMIR.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
Commit 42a9f6c554e378f1c010375eca30f04296aa0052 by Matthew.Arsenault
GlobalISel: Handle arbitrary FewerElementsVector for G_IMPLICIT_DEF
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
Commit 0c40af6b594f6eb2dcd43cdb2bc2f4584ec8ca15 by zinenko
[mlir] First-party modeling of LLVM types

The current modeling of LLVM IR types in MLIR is based on the LLVMType class
that wraps a raw `llvm::Type *` and delegates uniquing, printing and parsing to
LLVM itself. This model makes thread-safe type manipulation hard and is being
progressively replaced with a cleaner MLIR model that replicates the type
system.  Introduce a set of classes reflecting the LLVM IR type system in MLIR
instead of wrapping the existing types. These are currently introduced as
separate classes without affecting the dialect flow, and are exercised through
a test dialect. Once feature parity is reached, the old implementation will be
gradually substituted with the new one.

Depends On D84171

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D84339
The file was addedmlir/test/lib/Dialect/LLVMIR/LLVMTypeTestDialect.cpp
The file was addedmlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
The file was modifiedmlir/lib/Parser/DialectSymbolParser.cpp
The file was addedmlir/test/Dialect/LLVMIR/types-invalid.mlir
The file was modifiedmlir/include/mlir/IR/DialectImplementation.h
The file was modifiedmlir/tools/mlir-opt/CMakeLists.txt
The file was addedmlir/test/Dialect/LLVMIR/types.mlir
The file was addedmlir/lib/Dialect/LLVMIR/IR/TypeDetail.h
The file was addedmlir/test/lib/Dialect/LLVMIR/CMakeLists.txt
The file was addedmlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
The file was modifiedmlir/lib/Dialect/LLVMIR/CMakeLists.txt
The file was addedmlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
The file was modifiedmlir/tools/mlir-opt/mlir-opt.cpp
The file was modifiedmlir/test/lib/Dialect/CMakeLists.txt
Commit 2d8ca4ae2b1a512d31566e042a4bf4fa1043def9 by Xing
[DWARFYAML] Offsets should be omitted when the OffsetEntryCount is 0.

The offsets field should be omitted when the 'OffsetEntryCount' entry is
specified to be 0.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D85006
The file was modifiedllvm/test/tools/yaml2obj/ELF/DWARF/debug-rnglists.yaml
The file was modifiedllvm/lib/ObjectYAML/DWARFEmitter.cpp
Commit 23693ffc3ba6146a22cd1e9373e25dc1e1a41a17 by spatel
[InstCombine] reduce xor-of-or's bitwise logic (PR46955); 2nd try

The 1st try at this (rG2265d01f2a5b) exposed what looks like
unspecified behavior in C/C++ resulting in test variations.

The arguments to BinaryOperator::CreateAnd() were both IRBuilder
function calls, and the order in which they execute determines
the order of the new instructions in the IR. But the order of
function arg evaluation is not fixed by the rules of C/C++, so
depending on compiler config, the test would fail because the
test expected a single fixed ordering of instructions.

Original commit message:
I tried to use m_Deferred() on this, but didn't find
a clean way to do that.

http://bugs.llvm.org/PR46955

https://alive2.llvm.org/ce/z/2h6QTq
The file was modifiedllvm/test/Transforms/InstCombine/xor.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp