FailedChanges

Summary

  1. [ORC] Add operations to create and lookup JITDylibs to OrcV2 C bindings. (details)
  2. Revert "Do not apply calling conventions to MSVC entry points" (details)
  3. [AMDGPU] gfx1030 test update. NFC. (details)
  4. [NFC][LSAN] Change SuspendedThreadsList interface (details)
  5. [ELF] Bump the limit of thunk creation passes from 10 to 15 (details)
  6. [NFC][regalloc] type LiveInterval::reg() as Register (details)
  7. [obj2yaml] - Match ".stack_size" with the original section name, and not the uniquified name. (details)
  8. [lldb/test] Enable faulthandler in dotest (details)
  9. [NFC] Refactor DiagnosticBuilder and PartialDiagnostic (details)
  10. [libunwind] Support for leaf function unwinding. (details)
  11. [flang] Substrings with lower bound greater than upper bound (details)
  12. Disable a large test for EXPENSIVE_CHECKS and debug build (details)
  13. [AArch64] Add -mmark-bti-property flag. (details)
  14. [gn build] (manually) port 1321160a2 (details)
  15. [EarlyCSE] Simplify max/min pattern matching. NFC. (details)
  16. [Flang] Fixed installation permission of the "binary" flang (details)
  17. Commenting out atomics with padding to unbreak MSAN tests (details)
  18. Revert "[AArch64] Add -mmark-bti-property flag." (details)
  19. [AArch64] Add -mmark-bti-property flag. (details)
  20. [DAGCombiner] Teach visitMSTORE to replace an all ones mask with an unmasked store. (details)
  21. [MemorySSA] Rename uses in blocks with Phis. (details)
  22. Canonicalize declaration pointers when forming APValues. (details)
  23. PR47555: Inheriting constructors are implicitly definable. (details)
  24. [NewPM] Port -print-alias-sets to NPM (details)
  25. [IRSim] Adding IR Instruction Mapper (details)
  26. [mlir] expose affine map to C API (details)
  27. [gn build] Port b04c1a9d312 (details)
  28. [libunwind][DWARF] Fix end of .eh_frame calculation (details)
  29. [MachineSink] add one more mir case - nfc (details)
  30. [PowerPC] Fix store-fptoi combine of f128 on Power8 (details)
  31. Use zu rather than llu format specifier for size_t (-Wformat warning fix). (details)
  32. debug_rnglists/symbolizing: reduce memory usage by not caching rnglists (details)
  33. Revert "[IRSim] Adding IR Instruction Mapper" (details)
  34. [gn build] Port a895040eb02 (details)
  35. Flush bitcode incrementally for LTO output (details)
  36. Add the header of std::min (details)
  37. Fix the arguments of std::min (details)
  38. [lldb] Return FileSP and StreamFileSP by value in IOHandler (NFC) (details)
  39. Add __divmodti4 to match libgcc. (details)
  40. [llvm-cov gcov][test] Move tests to gcov/ (details)
  41. [DebugInfo] Simplify DIEInteger::SizeOf(). (details)
  42. [mlir][spirv] Add GroupNonUniformBroadcastOp (details)
  43. [llvm-cov gcov] Add --demangled-names (-m) (details)
  44. [mlir] Remove redundant shape.cstr_broadcastable canonicalization. (details)
  45. [SelectionDAG] Check any use of negation result before removal (details)
  46. [Lint] Add check for intrinsic get.active.lane.mask (details)
  47. [AMDGPU] Generate test checks for splitkit-copy-bundle.mir (details)
  48. [SplitKit] Only copy live lanes (details)
  49. [NFC] EliminateDuplicatePHINodes(): small-size optimization: if there are <= 32 PHI's, O(n^2) algo is faster (geomean -0.08%) (details)
  50. Revert "Re-land: Add new hidden option -print-changed which only reports changes to IR" (details)
  51. [X86] Fix stack alignment on 32-bit Solaris/x86 (details)
  52. [lldb] Don't send invalid region addresses to lldb server (details)
  53. [clang][aarch64] ACLE: Support implicit casts between GNU and SVE vectors (details)
  54. [mlir][Linalg] Convolution tiling added to ConvOp vectorization pass (details)
  55. [AsmPrinter] Remove orphan DwarfUnit::shareAcrossDWOCUs declaration. NFCI. (details)
  56. [AMDGPU] Remove orphan SITargetLowering::LowerINT_TO_FP declaration. NFCI. (details)
  57. [AsmPrinter] DwarfDebug - use DebugLoc const references where possible. NFC. (details)
  58. [MLIR] Turns swapId into a FlatAffineConstraints member func (details)
  59. [gn build] (manually) port c9af34027bc (details)
  60. [mlir] turn clang-format back on in C API test (details)
  61. [ARM] Extra fp16 bitcast tests. NFC (details)
  62. DwarfFile.h - remove unnecessary includes. NFCI. (details)
  63. DwarfStringPool.cpp - remove unnecessary StringRef include. NFCI. (details)
  64. [ARM] Additional tests for qr intrinsics in loops. NFC (details)
  65. Revert "[lldb] Don't send invalid region addresses to lldb server" (details)
  66. [NFC][ARM] Tail fold test changes (details)
  67. SymbolizableObjectFile.h - remove unnecessary includes. NFCI. (details)
  68. MetadataLoader.cpp - remove unnecessary StringRef include. NFCI. (details)
  69. [clang-format][regression][PR47461] ifdef causes catch to be seen as a function (details)
  70. [ConstraintSystem] Remove local variable that is set but not read [NFC] (details)
  71. Remove unnecessary forward declarations. NFCI. (details)
  72. [clang][docs] Fix documentation of -O (details)
  73. [SLP] sort candidates to increase chance of optimal compare reduction (details)
  74. [llvm-readelf/obj][test] - Document what we print in various places for unnamed section symbols. (details)
  75. [obj2yaml] - Don't emit EM_NONE. (details)
  76. [SVE][CodeGen] Lower floating point -> integer conversions (details)
  77. [MemorySSA] Add another loop clobber test case. (details)
  78. [ARM][MachineOutliner] Add missing testcase for calls. (details)
  79. InstCombiner.h - remove unnecessary KnownBits.h include. NFCI. (details)
  80. [AMDGPU] Bump to ROCm 3.7 dependency hip_hcc->amdhip64 (details)
  81. SafeStackLayout.cpp - remove unnecessary StackLifetime.h include. NFCI. (details)
  82. [compiler-rt] Avoid pulling libatomic to sanitizer tests (details)
  83. ValueList.cpp - remove unnecessary includes. NFCI. (details)
  84. DwarfExpression.cpp - remove unnecessary includes. NFCI. (details)
  85. LiveDebugVariables.cpp - remove unnecessary Compiler.h include. NFCI. (details)
  86. [compiler-rt] Replace INLINE with inline (details)
  87. [compiler-rt] [tsan] [netbsd] Catch unsupported LONG_JMP_SP_ENV_SLOT (details)
  88. [AMDGPU] should expand ROTL i16 to shifts. (details)
  89. [compiler-rt] [netbsd] Include <sys/dkbad.h> (details)
  90. [compiler-rt] [hwasan] Replace INLINE with inline (details)
  91. [mlir][Standard] Canonicalize chains of tensor_cast operations (details)
  92. [compiler-rt] [scudo] Fix typo in function attribute (details)
  93. [ARM] Sink splats to MVE intrinsics (details)
  94. [amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel. (details)
  95. [libc++] Remove some workarounds for missing variadic templates (details)
  96. [Coroutine] Fix a bug where Coroutine incorrectly spills phi and invoke defs before CoroBegin (details)
  97. [OpenMP 5.0] Fix user-defined mapper privatization in tasks (details)
  98. [DFSan] Add bcmp wrapper. (details)
  99. Precommit test updates (details)
  100. [AArch64] Match pairwise add/fadd pattern (details)
  101. [CUDA][HIP] Defer overloading resolution diagnostics for host device functions (details)
  102. [ARM] Add more MVE postinc distribution tests. NFC (details)
  103. [mlir][openacc] Change operand type from index to AnyInteger in parallel op (details)
  104. [flang][openacc] Lower clauses on loop construct to OpenACC dialect (details)
  105. [Test] Add tests showing that IndVars cannot prove (X + 1 > X) (details)
  106. Revert "[DFSan] Add bcmp wrapper." (details)
  107. ModuloSchedule.cpp - remove unnecessary includes. NFCI. (details)
  108. Fix build failure in clangd (details)
  109. [mlir][Vector] Add a folder for vector.broadcast (details)
  110. [AArch64][GlobalISel] Fix bug in fewVectorElts action while legalizing oversize G_FPTRUNC vectors. (details)
  111. [ARM] Expand distributing increments to also handle existing pre/post inc instructions. (details)
  112. [InstSimplify] add tests for FP constant miscompile; NFC (PR43907) (details)
  113. [amdgpu] Compilation fix for Release (details)
  114. [SyntaxTree][Synthesis] Fix allocation in `createTree` for more general use (details)
  115. [DFSan] Add bcmp wrapper. (details)
  116. [Sema] Introduce BuiltinAttr, per-declaration builtin-ness (details)
  117. [AMDGPU] Fix ROCm unit test memref initialization (details)
  118. Add missing include (details)
  119. [PowerPC][AIX] Don't hardcode python invoke command line (details)
  120. [VectorCombine] add test for multi-use load (PR47558); NFC (details)
  121. [VectorCombine] rearrange bailouts for load insert for efficiency; NFC (details)
  122. Revert "[CUDA][HIP] Defer overloading resolution diagnostics for host device functions" (details)
  123. Revert "[NFC] Refactor DiagnosticBuilder and PartialDiagnostic" (details)
  124. [MLIR] Support for return values in Affine.For yield (details)
  125. [MLIR][Affine] Add parametric tile size support for affine.for tiling (details)
  126. [X86] Don't match x87 register inline asm constraints unless the VT is floating point or its a clobber (details)
  127. [VectorCombine] limit load+insert transform to one-use (details)
  128. [AArch64][GlobalISel] Make <8 x s16> and <16 x s8> legal for shifts. (details)
  129. [AArch64][GlobalISel] Widen G_EXTRACT_VECTOR_ELT element types if < 8b. (details)
  130. [PDB] Split TypeServerSource and extend type index map lifetime (details)
  131. [SVE][WIP] Implement lowering for fixed length VSELECT to Scalable (details)
  132. [IRSim] Adding IR Instruction Mapper (details)
  133. [gn build] Port 7e4c6fb8546 (details)
  134. AArch64::ArchKind's underlying type is uint64_t (details)
  135. [Lsan] Use fp registers to search for pointers (details)
  136. Disable hoisting MI to hotter basic blocks when using pgo (details)
  137. [SCEV] Add test cases for max BTC with loop guard info. (details)
  138. [GVN] Add additional assume tests (NFC) (details)
  139. [GVN] Use that assume(!X) implies X==false (PR47496) (details)
  140. [LoopUnrollAndJam] Allow unroll and jam loops forced by user. (details)
  141. [InstCombine] Canonicalize SPF_ABS to abs intrinc (details)
  142. [llvm-install-name-tool] Update the command-line guide (details)
  143. [NewPM] Fix pr45927.ll under NPM (details)
  144. [MemorySSA] Be more conservative when traversing MemoryPhis. (details)
  145. Support dwarf fission for wasm object files (details)
  146. [TargetRegisterInfo] Add a couple of target hooks for the greedy register allocator (details)
  147. [test] Fix FullUnroll.ll (details)
  148. [AArch64] Enable implicit null check transformation (details)
  149. [RISCV] Support Shadow Call Stack (details)
  150. [MLIR][TableGen] Automatic detection and elimination of redundant methods (details)
  151. [MemorySSA] Fix an unused variable warning [NFC] (details)
  152. [PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang (details)
  153. [PowerPC] Add Set Boolean Condition Instruction Definitions and MC Tests (details)
  154. [AArch64][GlobalISel] clang-format AArch64LegalizerInfo.cpp. NFC. (details)
  155. [AArch64][GlobalISel] Make G_STORE <8 x s8> legal. (details)
  156. [lldb] Clarify docstring for SBBlock::IsInlined, NFC (details)
  157. [mlir][shape] Add `shape.cstr_require %bool` (details)
  158. [MLIR] Fix build failure due to https://reviews.llvm.org/D87059. (details)
  159. [scudo/standalone] Don't define test main function for Fuchsia (details)
  160. [NFC][Lsan] Fix zero-sized array compilation error (details)
  161. [NFC] clang-format one line (details)
  162. [sanitizer] Add facility to print the full StackDepot (details)
  163. [libc] Add implementation for hypotf (details)
  164. Revert "[sanitizer] Add facility to print the full StackDepot" (details)
  165. [AArch64] Emit zext move when the source of the zext is AssertZext or AssertSext (details)
Commit 9a0d1b66730c8761a5da59351bf1c7666958130b by Lang Hames
[ORC] Add operations to create and lookup JITDylibs to OrcV2 C bindings.
The file was modifiedllvm/lib/ExecutionEngine/Orc/OrcV2CBindings.cpp (diff)
The file was modifiedllvm/include/llvm-c/Orc.h (diff)
Commit bebfc3b92d5e8dd1b1d75d40d5d03975957eec14 by akhuang
Revert "Do not apply calling conventions to MSVC entry points"

This reverts commit 4cff1b40dacf6a5489b09657d94ea4757b8cd3b0.

Caused "undefined symbol: _WinMain@16" link errors.
The file was modifiedclang/lib/Sema/SemaDecl.cpp (diff)
The file was modifiedclang/test/CodeGenCXX/default_calling_conv.cpp (diff)
Commit a45cdb311f6e71fdf5452a4be9037f3fb028f1d1 by Stanislav.Mekhanoshin
[AMDGPU] gfx1030 test update. NFC.
The file was modifiedllvm/test/MC/AMDGPU/smem.s (diff)
Commit cd13476ab57b43b66831bba14206a350c5a4a81b by Vitaly Buka
[NFC][LSAN] Change SuspendedThreadsList interface

Remove RegisterCount and let GetRegistersAndSP to resize buffer as needed.

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D87747
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stoptheworld.h (diff)
The file was modifiedcompiler-rt/lib/lsan/lsan_common.cpp (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_mac.cpp (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_netbsd_libcdep.cpp (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp (diff)
Commit 15f0ad2fa29beaf1dad1548ccb97c2c729ea53cd by maskray
[ELF] Bump the limit of thunk creation passes from 10 to 15

I have noticed that a 374MiB powerpc64le 'ld.lld' requires 11 passes to link.
There is a ThunkSection (whose parent OutputSection is ".text" of 169MiB) with 12867 thunks.
The file was modifiedlld/ELF/Writer.cpp (diff)
Commit aa2ba67a8137040b9146d0383c74f0b75ac9683a by mtrofin
[NFC][regalloc] type LiveInterval::reg() as Register

We have the Register type which precisely captures the role of this
member. Storage-wise, it's an unsigned.

This helps readability & maintainability.

Differential Revision: https://reviews.llvm.org/D87768
The file was modifiedllvm/include/llvm/CodeGen/LiveInterval.h (diff)
Commit b1cb9d6271263b197ba53cac28a0fc3bf27ec5b8 by rahmanl
[obj2yaml] - Match ".stack_size" with the original section name, and not the uniquified name.

Without this patch, obj2yaml decodes the content of only one ".stack_size" section. Other sections are dumped with their full contents.

Reviewed By: grimar, MaskRay

Differential Revision: https://reviews.llvm.org/D87727
The file was modifiedllvm/test/tools/obj2yaml/ELF/stack-sizes.yaml (diff)
The file was modifiedllvm/tools/obj2yaml/elf2yaml.cpp (diff)
Commit dd67581407c1693e43ac8a90b3a20c597614bda8 by rupprecht
[lldb/test] Enable faulthandler in dotest

Register the `faulthandler` module so we can see what lldb tests are doing when they misbehave (e.g. run under a test runner that sets a timeout). This will print a stack trace for the following signals:

- `SIGSEGV`, `SIGFPE`, `SIGABRT`, `SIGBUS`, and `SIGILL` (via `faulthandler.enable()`)
- `SIGTERM` (via `faulthandler.register(SIGTERM)`) [This is what our test runners sends when it times out].

The only signal we currently handle is `SIGINT` (via `unittest2.signals.installHandler()`) so there should be no overlap added by this patch.

Because this import is not available until python3, and the `register()` method is not available on Windows, this is enabled defensively.

This should have absolutely no effect when tests are passing (or even normally failing), but can be observed by running this while ninja is running:

```
kill -s SIGTERM $(ps aux | grep dotest.py | head -1 | awk '{print $2}')
```

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D87637
The file was modifiedlldb/packages/Python/lldbsuite/test/dotest.py (diff)
Commit ee5519d323571c4a9a7d92cb817023c9b95334cd by Yaxun.Liu
[NFC] Refactor DiagnosticBuilder and PartialDiagnostic

PartialDiagnostic misses some functions compared to DiagnosticBuilder.

This patch refactors DiagnosticBuilder and PartialDiagnostic, extracts
the common functionality so that the streaming << operators are
shared.

Differential Revision: https://reviews.llvm.org/D84362
The file was modifiedclang/include/clang/AST/TemplateBase.h (diff)
The file was modifiedclang/lib/AST/ASTContext.cpp (diff)
The file was modifiedclang/include/clang/Basic/PartialDiagnostic.h (diff)
The file was modifiedclang/include/clang/AST/DeclCXX.h (diff)
The file was modifiedclang/include/clang/AST/DeclarationName.h (diff)
The file was modifiedclang/include/clang/AST/TemplateName.h (diff)
The file was modifiedclang/include/clang/AST/Decl.h (diff)
The file was modifiedclang/include/clang/Sema/Ownership.h (diff)
The file was modifiedclang/include/clang/Sema/Sema.h (diff)
The file was modifiedclang/lib/AST/DeclCXX.cpp (diff)
The file was modifiedclang/include/clang/AST/Type.h (diff)
The file was modifiedclang/include/clang/Basic/Diagnostic.h (diff)
The file was modifiedclang/lib/AST/TemplateName.cpp (diff)
The file was modifiedclang/lib/Basic/Diagnostic.cpp (diff)
The file was modifiedclang/include/clang/AST/ASTContext.h (diff)
The file was modifiedclang/include/clang/AST/NestedNameSpecifier.h (diff)
The file was modifiedclang/lib/AST/TemplateBase.cpp (diff)
The file was modifiedclang/include/clang/AST/CanonicalType.h (diff)
The file was modifiedclang/include/clang/AST/Attr.h (diff)
The file was modifiedclang/include/clang/Sema/ParsedAttr.h (diff)
Commit 23bef7ee9923b1262326981960397e8cd95d6923 by daniel.kiss
[libunwind] Support for leaf function unwinding.

Unwinding leaf function is useful in cases when the backtrace finds a
leaf function for example when it caused a signal.
This patch also add the support for the DW_CFA_undefined because it marks
the end of the frames.

Ryan Prichard provided code for the tests.

Reviewed By: #libunwind, mstorsjo

Differential Revision: https://reviews.llvm.org/D83573
The file was modifiedlibunwind/src/DwarfParser.hpp (diff)
The file was modifiedlibunwind/src/DwarfInstructions.hpp (diff)
The file was modifiedlibunwind/test/lit.site.cfg.in (diff)
The file was addedlibunwind/test/signal_unwind.pass.cpp
The file was addedlibunwind/test/unwind_leaffunction.pass.cpp
Commit dd3eb3f33239b23a12dd8864ae236390adf79550 by psteinfeld
[flang] Substrings with lower bound greater than upper bound

According to section 9.4.1, paragraph 3,
If the starting point is greater than the ending point, the substring has
length zero

But the compilers code for substring processing was failing a call to `CHECK()`
in this case.  I fixed this by just setting the number of items in the
resulting string to 0 for this situation.

Differential Revision: https://reviews.llvm.org/D87799
The file was modifiedflang/lib/Evaluate/variable.cpp (diff)
The file was modifiedflang/test/Semantics/resolve49.f90 (diff)
Commit 1321160a26e7e489baf9b10d6de90a342f898960 by jasonliu
Disable a large test for EXPENSIVE_CHECKS and debug build

Summary:
When running a large test in LLVM_ENABLE_EXPENSIVE_CHECKS=ON mode,
buildbot could hit timeout.
Disable the test when this mode is on.
Also disable it for debug so that the test won't hang for too long.

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D87794
The file was modifiedllvm/test/lit.site.cfg.py.in (diff)
The file was modifiedllvm/test/lit.cfg.py (diff)
The file was modifiedllvm/test/CMakeLists.txt (diff)
The file was modifiedllvm/test/CodeGen/PowerPC/aix-overflow-toc.py (diff)
Commit 95e43f84b7b9c61011aece7583c0367297dd67d8 by daniel.kiss
[AArch64] Add -mmark-bti-property flag.

Writing the .note.gnu.property manually is error prone and hard to
maintain in the assembly files.
The -mmark-bti-property is for the assembler to emit the section with the
GNU_PROPERTY_AARCH64_FEATURE_1_BTI. To be used when C/C++ is compiled
with -mbranch-protection=bti.

This patch refactors the .note.gnu.property handling.

Reviewed By: chill, nickdesaulniers

Differential Revision: https://reviews.llvm.org/D81930
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp (diff)
The file was modifiedclang/include/clang/Driver/Options.td (diff)
The file was addedclang/test/Driver/arm64-markbti.S
The file was modifiedllvm/lib/Target/AArch64/AArch64AsmPrinter.cpp (diff)
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp (diff)
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h (diff)
Commit 0c6a56e41dbeb9ffc47ca0b03357f15cb5d30689 by thakis
[gn build] (manually) port 1321160a2
The file was modifiedllvm/utils/gn/secondary/llvm/test/BUILD.gn (diff)
Commit 4e4c89b22c3fc1200ee0d6d1074173c7c53d87bc by michael.hliao
[EarlyCSE] Simplify max/min pattern matching. NFC.
The file was modifiedllvm/lib/Transforms/Scalar/EarlyCSE.cpp (diff)
Commit d89c5ae8577264f5dd660906f12577c5fdadf49e by tianshilei1992
[Flang] Fixed installation permission of the "binary" flang

Under current configuration, the permission of `flang` after installation is 700.
This could bring a problem for system administrators who build and install flang
for other users, which only the user who builds LLVM can execute it, and others
can not. In this patch, the explicit permission setting in the `install` command
is removed, and let CMake determine what perssion to be used like other components.

Reviewed By: DavidTruby

Differential Revision: https://reviews.llvm.org/D87783
The file was modifiedflang/tools/f18/CMakeLists.txt (diff)
Commit 5b205ff474120e086435724dc04f784b784fdd1a by ogiroux
Commenting out atomics with padding to unbreak MSAN tests
The file was modifiedlibcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.req/atomic_helpers.h (diff)
Commit 60e244f82c1f97c1b7d65c06d2b0b4f634f8d696 by daniel.kiss
Revert "[AArch64] Add -mmark-bti-property flag."

This reverts commit 95e43f84b7b9c61011aece7583c0367297dd67d8.
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp (diff)
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64AsmPrinter.cpp (diff)
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp (diff)
The file was modifiedclang/include/clang/Driver/Options.td (diff)
The file was removedclang/test/Driver/arm64-markbti.S
Commit f70baaf71f62ba8623b3522345527271add74f6b by daniel.kiss
[AArch64] Add -mmark-bti-property flag.

Writing the .note.gnu.property manually is error prone and hard to
maintain in the assembly files.
The -mmark-bti-property is for the assembler to emit the section with the
GNU_PROPERTY_AARCH64_FEATURE_1_BTI. To be used when C/C++ is compiled
with -mbranch-protection=bti.

This patch refactors the .note.gnu.property handling.

Reviewed By: chill, nickdesaulniers

Differential Revision: https://reviews.llvm.org/D81930

Reland with test dependency on aarch64 target.
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp (diff)
The file was addedclang/test/Driver/arm64-markbti.S
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64AsmPrinter.cpp (diff)
The file was modifiedclang/include/clang/Driver/Options.td (diff)
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h (diff)
Commit e30371d99d5157ac9718c803dd1101f9cbb1b224 by craig.topper
[DAGCombiner] Teach visitMSTORE to replace an all ones mask with an unmasked store.

Similar to what done in D87788 for MLOAD.

Again I've skipped indexed, truncating, and compressing stores.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (diff)
The file was modifiedllvm/test/CodeGen/X86/masked_store.ll (diff)
Commit 344a3d0bc0fb0868b519c3342b4982d6121eece3 by asbirlea
[MemorySSA] Rename uses in blocks with Phis.

Renaming should include blocks with existing Phis.

Resolves PR45927.

Differential Revision: https://reviews.llvm.org/D87661
The file was addedllvm/test/Analysis/MemorySSA/pr45927.ll
The file was modifiedllvm/lib/Analysis/MemorySSAUpdater.cpp (diff)
Commit 905b9ca26c94fa86339451a528cedde5004fc1bb by richard
Canonicalize declaration pointers when forming APValues.

References to different declarations of the same entity aren't different
values, so shouldn't have different representations.

Recommit of e6393ee813178e9d3306b8e3c6949a4f32f8a2cb with fixed
handling for weak declarations. We now look for attributes on the most
recent declaration when determining whether a declaration is weak.
The file was modifiedclang/include/clang/AST/APValue.h (diff)
The file was modifiedclang/test/CXX/dcl.dcl/dcl.spec/dcl.constexpr/p9.cpp (diff)
The file was modifiedclang/test/OpenMP/ordered_messages.cpp (diff)
The file was modifiedclang/lib/AST/APValue.cpp (diff)
The file was modifiedclang/lib/AST/Decl.cpp (diff)
The file was modifiedclang/lib/AST/DeclBase.cpp (diff)
The file was modifiedclang/lib/AST/ExprConstant.cpp (diff)
Commit 7337f296194483e0959ff980049e2835e226f396 by richard
PR47555: Inheriting constructors are implicitly definable.

Don't forget to define them if they're constexpr and used inside a
template; we might try to evaluate a call to them before the template is
instantiated.
The file was modifiedclang/test/SemaCXX/cxx11-inheriting-ctors.cpp (diff)
The file was modifiedclang/lib/Sema/SemaExpr.cpp (diff)
Commit f4ea0f98142a97666cd0478757570e819923a829 by aeubanks
[NewPM] Port -print-alias-sets to NPM

Really it should be named print<alias-sets>, but for the sake of
changing fewer tests, added a TODO to rename after NPM switch and test
cleanup.

Reviewed By: ychen

Differential Revision: https://reviews.llvm.org/D87713
The file was modifiedllvm/lib/Analysis/AliasSetTracker.cpp (diff)
The file was modifiedllvm/test/Analysis/AliasSet/guards.ll (diff)
The file was modifiedllvm/lib/Passes/PassBuilder.cpp (diff)
The file was modifiedllvm/lib/Passes/PassRegistry.def (diff)
The file was modifiedllvm/include/llvm/Analysis/AliasSetTracker.h (diff)
Commit b04c1a9d3127730c05e8a22a0e931a12a39528df by andrew_litteken
[IRSim] Adding IR Instruction Mapper

This introduces the IRInstructionMapper, and the associated wrapper for
instructions, IRInstructionData, that maps IR level Instructions to
unsigned integers.

Mapping is done mainly by using the "isSameOperationAs" comparison
between two instructions.  If they return true, the opcode, result type,
and operand types of the instruction are used to hash the instruction
with an unsigned integer.  The mapper accepts instruction ranges, and
adds each resulting integer to a list, and each wrapped instruction to
a separate list.

At present, branches, phi nodes are not mapping and exception handling
is illegal.  Debug instructions are not considered.

The different mapping schemes are tested in
unittests/Analysis/IRSimilarityIdentifierTest.cpp

Differential Revision: https://reviews.llvm.org/D86968
The file was modifiedllvm/unittests/Analysis/CMakeLists.txt (diff)
The file was addedllvm/include/llvm/Analysis/IRSimilarityIdentifier.h
The file was addedllvm/unittests/Analysis/IRSimilarityIdentifierTest.cpp
The file was addedllvm/lib/Analysis/IRSimilarityIdentifier.cpp
The file was modifiedllvm/lib/Analysis/CMakeLists.txt (diff)
Commit b76f523be6ea606d9cf494e247546cec1cd7f209 by zhanghb97
[mlir] expose affine map to C API

This patch provides C API for MLIR affine map.
- Implement C API for AffineMap class.
- Add Utils.h to include/mlir/CAPI/, and move the definition of the CallbackOstream to Utils.h to make sure mlirAffineMapPrint work correct.
- Add TODO for exposing the C API related to AffineExpr and mutable affine map.

Differential Revision: https://reviews.llvm.org/D87617
The file was addedmlir/include/mlir/CAPI/Utils.h
The file was modifiedmlir/lib/CAPI/IR/AffineMap.cpp (diff)
The file was modifiedmlir/lib/CAPI/IR/IR.cpp (diff)
The file was modifiedmlir/test/CAPI/ir.c (diff)
The file was modifiedmlir/include/mlir-c/AffineMap.h (diff)
Commit 436a43afb2cf85ae6e61b4c1ac09e944a6566646 by llvmgnsyncbot
[gn build] Port b04c1a9d312
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Analysis/BUILD.gn (diff)
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/Analysis/BUILD.gn (diff)
Commit fb1abe00635c1ec28e55921709904d5ca2e86a74 by rprichard
[libunwind][DWARF] Fix end of .eh_frame calculation

* When .eh_frame is located using .eh_frame_hdr (PT_GNU_EH_FRAME), the
   start of .eh_frame is known, but not the size. In this case, the
   unwinder must rely on a terminator present at the end of .eh_frame.
   Set dwarf_section_length to UINTPTR_MAX to indicate this.

* Add a new field, text_segment_length, that the FrameHeaderCache uses
   to track the size of the PT_LOAD segment indicated by dso_base.

* Compute ehSectionEnd by adding sectionLength to ehSectionStart,
   never to fdeHint.

Fixes PR46829.

Differential Revision: https://reviews.llvm.org/D87750
The file was modifiedlibunwind/src/UnwindCursor.hpp (diff)
The file was modifiedlibunwind/src/FrameHeaderCache.hpp (diff)
The file was modifiedlibunwind/src/DwarfParser.hpp (diff)
The file was modifiedlibunwind/src/AddressSpace.hpp (diff)
The file was modifiedlibunwind/test/frameheadercache_test.pass.cpp (diff)
Commit 5782ab0f52db1b1914d8ee5fe3828b0a5de9d685 by czhengsz
[MachineSink] add one more mir case - nfc
The file was addedllvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir
Commit ebfbdebe9678f4a42ec35396eb517eefd85d2b4c by qiucofan
[PowerPC] Fix store-fptoi combine of f128 on Power8

llc would crash for (store (fptosi-f128-i32)) when -mcpu=pwr8, we should
not generate FP_TO_(S|U)INT_IN_VSR for f128 types at this time. This
patch fixes it.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D86686
The file was modifiedllvm/test/CodeGen/PowerPC/store_fptoi.ll (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp (diff)
Commit c140322819806cb292e079d62f2e9dbab697c08c by echristo
Use zu rather than llu format specifier for size_t (-Wformat warning fix).
The file was modifiedlldb/source/Expression/REPL.cpp (diff)
Commit 6a07f1edf8e6a172734286cd3ab5988313313d8f by dblaikie
debug_rnglists/symbolizing: reduce memory usage by not caching rnglists

This matches the debug_ranges behavior - though is currently implemented
differently. (the debug_ranges parsing was handled by creating a new
ranges parser during DIE address querying, and just destroying it after
the query - whereas the rnglists parser is a member of the DWARFUnit
currently - so the API doesn't cache anymore)

I think this could/should be improved by not parsing debug_rnglists
headers at all when dumping debug_info or symbolizing - do it the way
DWARF (roughly) intended: take the rnglists_base, add addr*index to it,
read the offset, parse the list at rnglists_base+offset. This would have
no error checking for valid index (because the number of valid indexes
is stored in the header, which has a negative offset from rnglists_base
- and is sort of only intended for use by dumpers, not by parsers going
from debug_info to a rnglist) or out of contribution bounds access
(since it wouldn't know the length of the contribution, also in the
header) - nor any error-checking that the rnglist contribution was using
the same properties as the debug_info (version, DWARF32/64, address
size, etc).
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFListTable.h (diff)
Commit a895040eb022b8a621d8e85754f113d82e232ab1 by stilis
Revert "[IRSim] Adding IR Instruction Mapper"

This reverts commit b04c1a9d3127730c05e8a22a0e931a12a39528df.
The file was removedllvm/include/llvm/Analysis/IRSimilarityIdentifier.h
The file was removedllvm/unittests/Analysis/IRSimilarityIdentifierTest.cpp
The file was modifiedllvm/lib/Analysis/CMakeLists.txt (diff)
The file was modifiedllvm/unittests/Analysis/CMakeLists.txt (diff)
The file was removedllvm/lib/Analysis/IRSimilarityIdentifier.cpp
Commit 0dd4d70ec20cebb951bd2e0e6525b056fb8dc86c by llvmgnsyncbot
[gn build] Port a895040eb02
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/Analysis/BUILD.gn (diff)
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Analysis/BUILD.gn (diff)
Commit 11201315d5881a135faa5aa87f415ce03f99eb96 by jianzhouzh
Flush bitcode incrementally for LTO output

Bitcode writer does not flush buffer until the end by default. This is
fine to small bitcode files. When -flto,--plugin-opt=emit-llvm,-gmlt are
used, the final bitcode file is large, for example, >8G. Keeping all
data in memory consumes a lot of memory.

This change allows bitcode writer flush data to disk early when buffered
data size is above some threshold. This is only enabled when lld emits
LLVM bitcode.

One issue to address is backpatching bitcode: subblock length, function
body indexes, meta data indexes need to backfill. If buffer can be
flushed partially, we introduced raw_fd_stream that supports
read/seek/write, and enables backpatching bitcode flushed in disk.

Reviewed-by: tejohnson, MaskRay

Differential Revision: https://reviews.llvm.org/D86905
The file was modifiedllvm/include/llvm/Bitstream/BitstreamWriter.h (diff)
The file was modifiedllvm/include/llvm/Bitcode/BitcodeWriter.h (diff)
The file was modifiedlld/ELF/LTO.cpp (diff)
The file was modifiedllvm/lib/Bitcode/Writer/BitcodeWriter.cpp (diff)
Commit 352a55ef06a9dcb3dfeb45302e9789da24b513c3 by jianzhouzh
Add the header of std::min

fixing
https://github.com/llvm/llvm-project/commit/11201315d5881a135faa5aa87f415ce03f99eb96
The file was modifiedllvm/include/llvm/Bitstream/BitstreamWriter.h (diff)
Commit aec80c5cfd1bda8e630fca0f3ed2a84659f68635 by jianzhouzh
Fix the arguments of std::min

fixing
https://github.com/llvm/llvm-project/commit/11201315d5881a135faa5aa87f415ce03f99eb96
The file was modifiedllvm/include/llvm/Bitstream/BitstreamWriter.h (diff)
Commit 57dd92746a53526bd7a86c1cfc7c0dce57a2e170 by Jonas Devlieghere
[lldb] Return FileSP and StreamFileSP by value in IOHandler (NFC)

Smart pointers should be returned by value.
The file was modifiedlldb/include/lldb/Core/IOHandler.h (diff)
The file was modifiedlldb/source/Core/IOHandler.cpp (diff)
Commit c9af34027bc9cb852a4e5e96154a7bd89531a6de by craig.topper
Add __divmodti4 to match libgcc.

gcc has used this on x86-64 since at least version 7.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D80506
The file was modifiedcompiler-rt/lib/builtins/README.txt (diff)
The file was modifiedcompiler-rt/lib/builtins/CMakeLists.txt (diff)
The file was addedcompiler-rt/test/builtins/Unit/divmodti4_test.c
The file was addedcompiler-rt/lib/builtins/divmodti4.c
Commit e69092be5247937213865289013185811d0fbc5e by i
[llvm-cov gcov][test] Move tests to gcov/

And rename llvm-cov.test (misnomer) to basic.test
The file was addedllvm/test/tools/llvm-cov/gcov/gcov-8.c
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/test.gcno
The file was addedllvm/test/tools/llvm-cov/gcov/gcov-9.c
The file was removedllvm/test/tools/llvm-cov/Inputs/gcov-8.gcda
The file was removedllvm/test/tools/llvm-cov/Inputs/test_no_gcda.cpp.gcov
The file was removedllvm/test/tools/llvm-cov/gcov-intermediate-format.test
The file was addedllvm/test/tools/llvm-cov/gcov/gcov-4.7.c
The file was removedllvm/test/tools/llvm-cov/Inputs/test_func_checksum_fail.gcda
The file was removedllvm/test/tools/llvm-cov/Inputs/test.gcda
The file was removedllvm/test/tools/llvm-cov/Inputs/test.gcno
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/test_read_fail.gcno
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/gcov-fake-4.2.gcda
The file was removedllvm/test/tools/llvm-cov/Inputs/test.h
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/gcov-4.7.gcda
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/test_paths.gcno
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/test_no_options.h.gcov
The file was removedllvm/test/tools/llvm-cov/Inputs/test_file_checksum_fail.gcda
The file was removedllvm/test/tools/llvm-cov/Inputs/gcov-4.7.gcda
The file was removedllvm/test/tools/llvm-cov/Inputs/gcov-4.7.gcno
The file was removedllvm/test/tools/llvm-cov/Inputs/test_no_gcda.h.gcov
The file was removedllvm/test/tools/llvm-cov/gcov-fake-4.2.c
The file was removedllvm/test/tools/llvm-cov/Inputs/gcov-fake-4.2.gcda
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/test_no_gcda.h.gcov
The file was removedllvm/test/tools/llvm-cov/Inputs/test_no_options.cpp.gcov
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/gcov-9.gcda
The file was removedllvm/test/tools/llvm-cov/Inputs/gcov-9.gcno
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/test_file_checksum_fail.gcda
The file was removedllvm/test/tools/llvm-cov/gcov-8.c
The file was addedllvm/test/tools/llvm-cov/gcov/basic.test
The file was removedllvm/test/tools/llvm-cov/gcov-4.7.c
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/test.cpp
The file was addedllvm/test/tools/llvm-cov/gcov/gcov-fake-4.2.c
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/gcov-fake-4.2.gcno
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/test.gcda
The file was removedllvm/test/tools/llvm-cov/llvm-cov.test
The file was removedllvm/test/tools/llvm-cov/Inputs/test_no_options.h.gcov
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/test_paths.gcda
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/test_func_checksum_fail.gcda
The file was removedllvm/test/tools/llvm-cov/Inputs/gcov-fake-4.2.gcno
The file was removedllvm/test/tools/llvm-cov/Inputs/test_read_fail.gcno
The file was addedllvm/test/tools/llvm-cov/gcov/intermediate-format.test
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/gcov-8.gcda
The file was removedllvm/test/tools/llvm-cov/gcov-9.c
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/gcov-8.gcno
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/gcov-9.gcno
The file was removedllvm/test/tools/llvm-cov/Inputs/test.cpp
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/test.h
The file was removedllvm/test/tools/llvm-cov/Inputs/test_paths.gcda
The file was removedllvm/test/tools/llvm-cov/Inputs/gcov-9.gcda
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/gcov-4.7.gcno
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/test_no_gcda.cpp.gcov
The file was addedllvm/test/tools/llvm-cov/gcov/Inputs/test_no_options.cpp.gcov
The file was removedllvm/test/tools/llvm-cov/Inputs/test_paths.gcno
The file was removedllvm/test/tools/llvm-cov/Inputs/gcov-8.gcno
Commit 027d47d1c7ce1708294f5273cde09b24c7cbab77 by ikudrin
[DebugInfo] Simplify DIEInteger::SizeOf().

An AsmPrinter should always be provided to the method because some forms
depend on its parameters. The only place in the codebase which passed
a nullptr value was found in the unit tests, so the patch updates it to
use some dummy AsmPrinter instead.

Differential Revision: https://reviews.llvm.org/D85293
The file was modifiedllvm/unittests/CodeGen/DIEHashTest.cpp (diff)
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DIE.cpp (diff)
Commit 4ce84b0e704ee7b8b13e236e65b3bf49da27a91c by thomasraoux
[mlir][spirv] Add GroupNonUniformBroadcastOp

Added GroupNonUniformBroadcastOp to spirv dialect.

Differential Revision: https://reviews.llvm.org/D87688
The file was modifiedmlir/include/mlir/Dialect/SPIRV/SPIRVNonUniformOps.td (diff)
The file was modifiedmlir/test/Dialect/SPIRV/non-uniform-ops.mlir (diff)
The file was modifiedmlir/test/Dialect/SPIRV/Serialization/non-uniform-ops.mlir (diff)
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVOps.cpp (diff)
The file was modifiedmlir/include/mlir/Dialect/SPIRV/SPIRVBase.td (diff)
Commit c16417f65f9a9eb3718efa3ece63ba910f91f77b by i
[llvm-cov gcov] Add --demangled-names (-m)

gcov 4.9 introduced the option.
The file was modifiedllvm/tools/llvm-cov/gcov.cpp (diff)
The file was modifiedllvm/lib/ProfileData/LLVMBuild.txt (diff)
The file was modifiedllvm/include/llvm/ProfileData/GCOV.h (diff)
The file was addedllvm/test/tools/llvm-cov/gcov/demangled-names.test
The file was modifiedllvm/lib/ProfileData/GCOV.cpp (diff)
Commit b05629230e9c7e90a2e70a761f7800afb1a8eefd by tpopp
[mlir] Remove redundant shape.cstr_broadcastable canonicalization.

These canonicalizations are already handled by folding which will occur
in a superset of situations, so they are being removed.

Differential Revision: https://reviews.llvm.org/D87706
The file was modifiedmlir/lib/Dialect/Shape/IR/Shape.cpp (diff)
Commit a2fb5446be960ad164060b3c05fc268f7f72d67a by qiucofan
[SelectionDAG] Check any use of negation result before removal

2508ef01 fixed a bug about constant removal in negation. But after
sanitizing check I found there's still some issue about it so it's
reverted.

Temporary nodes will be removed if useless in negation. Before the
removal, they'd be checked if any other nodes used it. So the removal
was moved after getNode. However in rare cases the node to be removed is
the same as result of getNode. We missed that and will be fixed by this
patch.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D87614
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (diff)
The file was addedllvm/test/CodeGen/X86/pr47517.ll
Commit 6637d72ddd3cf4cf3a7e6dfc227a86999137badb by sjoerd.meijer
[Lint] Add check for intrinsic get.active.lane.mask

As @efriedma pointed out in D86301, this "not equal to 0 check" of
get.active.lane.mask's second operand needs to live here in Lint and not the
Verifier.

Differential Revision: https://reviews.llvm.org/D87228
The file was addedllvm/test/Analysis/Lint/get-active-lane-mask.ll
The file was modifiedllvm/lib/Analysis/Lint.cpp (diff)
Commit d49707cf4b288e8d3cad00a78cfa45ec4c376496 by jay.foad
[AMDGPU] Generate test checks for splitkit-copy-bundle.mir

This is a pre-commit for D87757 "[SplitKit] Only copy live lanes".
The file was modifiedllvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir (diff)
Commit 6f6d389da5c37e5e9a900902f03dc649d57919b7 by jay.foad
[SplitKit] Only copy live lanes

When splitting a live interval with subranges, only insert copies for
the lanes that are live at the point of the split. This avoids some
unnecessary copies and fixes a problem where copying dead lanes was
generating MIR that failed verification. The test case for this is
test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir.

Without this fix, some earlier live range splitting would create %430:

%430 [256r,848r:0)[848r,2584r:1)  0@256r 1@848r L0000000000000003 [848r,2584r:0)  0@848r L0000000000000030 [256r,2584r:0)  0@256r weight:1.480938e-03
...
256B     undef %430.sub2:vreg_128 = V_LSHRREV_B32_e32 16, %20.sub1:vreg_128, implicit $exec
...
848B     %430.sub0:vreg_128 = V_AND_B32_e32 %92:sreg_32, %20.sub1:vreg_128, implicit $exec
...
2584B    %431:vreg_128 = COPY %430:vreg_128

Then RAGreedy::tryLocalSplit would split %430 into %432 and %433 just
before 848B giving:

%432 [256r,844r:0)  0@256r L0000000000000030 [256r,844r:0)  0@256r weight:3.066802e-03
%433 [844r,848r:0)[848r,2584r:1)  0@844r 1@848r L0000000000000030 [844r,2584r:0)  0@844r L0000000000000003 [844r,844d:0)[848r,2584r:1)  0@844r 1@848r weight:2.831776e-03
...
256B     undef %432.sub2:vreg_128 = V_LSHRREV_B32_e32 16, %20.sub1:vreg_128, implicit $exec
...
844B     undef %433.sub0:vreg_128 = COPY %432.sub0:vreg_128 {
           internal %433.sub2:vreg_128 = COPY %432.sub2:vreg_128
848B     }
  %433.sub0:vreg_128 = V_AND_B32_e32 %92:sreg_32, %20.sub1:vreg_128, implicit $exec
...
2584B    %431:vreg_128 = COPY %433:vreg_128

Note that the copy from %432 to %433 at 844B is a curious
bundle-without-a-BUNDLE-instruction that SplitKit creates deliberately,
and it includes a copy of .sub0 which is not live at this point, and
that causes it to fail verification:

*** Bad machine code: No live subrange at use ***
- function:    zextload_global_v64i16_to_v64i64
- basic block: %bb.0  (0x7faed48) [0B;2848B)
- instruction: 844B    undef %433.sub0:vreg_128 = COPY %432.sub0:vreg_128
- operand 1:   %432.sub0:vreg_128
- interval:    %432 [256r,844r:0)  0@256r L0000000000000030 [256r,844r:0)  0@256r weight:3.066802e-03
- at:          844B

Using real bundles with a BUNDLE instruction might also fix this
problem, but the current fix is less invasive and also avoids some
unnecessary copies.

https://bugs.llvm.org/show_bug.cgi?id=47492

Differential Revision: https://reviews.llvm.org/D87757
The file was modifiedllvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir (diff)
The file was modifiedllvm/lib/CodeGen/SplitKit.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll (diff)
The file was addedllvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
Commit aadf55d1cea24a4e5384ab8546c3d794cb1ec724 by lebedev.ri
[NFC] EliminateDuplicatePHINodes(): small-size optimization: if there are <= 32 PHI's, O(n^2) algo is faster (geomean -0.08%)

This is functionally equivalent to the old implementation.

As per https://llvm-compile-time-tracker.com/compare.php?from=5f4e9bf6416e45eba483a4e5e263749989fdb3b3&to=4739e6e4eb54d3736e6457249c0919b30f6c855a&stat=instructions
this is a clear geomean compile-time regression-free win with overall geomean of `-0.08%`

32 PHI's appears to be the sweet spot; both the 16 and 64 performed worse:
https://llvm-compile-time-tracker.com/compare.php?from=5f4e9bf6416e45eba483a4e5e263749989fdb3b3&to=c4efe1fbbfdf0305ac26cd19eacb0c7774cdf60e&stat=instructions
https://llvm-compile-time-tracker.com/compare.php?from=5f4e9bf6416e45eba483a4e5e263749989fdb3b3&to=e4989d1c67010d3339d1a40ff5286a31f10cfe82&stat=instructions

If we have more PHI's than that, we fall-back to the original DenseSet-based implementation,
so the not-so-fast cases will still be handled.

However compile-time isn't the main motivation here.
I can name at least 3 limitations of this CSE:
1. Assumes that all PHI nodes have incoming basic blocks in the same order (can be fixed while keeping the DenseMap)
2. Does not special-handle `undef` incoming values (i don't see how we can do this with hashing)
3. Does not special-handle backedge incoming values (maybe can be fixed by hashing backedge as some magical value)

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D87408
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp (diff)
Commit b03c2b8395ba94fb53f1e73a6473faedf628bbd9 by douglas.yung
Revert "Re-land: Add new hidden option -print-changed which only reports changes to IR"

The test added in this commit is failing on Windows bots:

http://lab.llvm.org:8011/builders/llvm-clang-win-x-armv7l/builds/1269

This reverts commit f9e6d1edc0dad9afb26e773aa125ed62c58f7080 and follow-up commit 6859d95ea2d0f3fe0de2923a3f642170e66a1a14.
The file was modifiedllvm/include/llvm/Passes/StandardInstrumentations.h (diff)
The file was modifiedllvm/lib/Passes/StandardInstrumentations.cpp (diff)
The file was removedllvm/test/Other/change-printer.ll
The file was modifiedllvm/lib/IR/LegacyPassManager.cpp (diff)
Commit a9cbe5cf30e386a4f44981f5bf9e1862ad36574d by ro
[X86] Fix stack alignment on 32-bit Solaris/x86

On Solaris/x86, several hundred 32-bit tests `FAIL`, all in the same way:

  env ASAN_OPTIONS=halt_on_error=false ./halt_on_error_suppress_equal_pcs.cpp.tmp
  Segmentation Fault (core dumped)

They segfault during startup:

  Thread 2 received signal SIGSEGV, Segmentation fault.
  [Switching to Thread 1 (LWP 1)]
  0x080f21f0 in __sanitizer::internal_mmap(void*, unsigned long, int, int, int, unsigned long long) () at /vol/llvm/src/llvm-project/dist/compiler-rt/lib/sanitizer_common/sanitizer_solaris.cpp:65
  65                              int prot, int flags, int fd, OFF_T offset) {
  1: x/i $pc
  => 0x80f21f0 <_ZN11__sanitizer13internal_mmapEPvmiiiy+16>: movaps 0x30(%esp),%xmm0
  (gdb) p/x $esp
  $3 = 0xfeffd488

The problem is that `movaps` expects 16-byte alignment, while 32-bit Solaris/x86
only guarantees 4-byte alignment following the i386 psABI.

This patch updates `X86Subtarget::initSubtargetFeatures` accordingly,
handles Solaris/x86 in the corresponding testcase, and allows for some
variation in address alignment in
`compiler-rt/test/ubsan/TestCases/TypeCheck/vptr.cpp`.

Tested on `amd64-pc-solaris2.11` and `x86_64-pc-linux-gnu`.

Differential Revision: https://reviews.llvm.org/D87615
The file was modifiedllvm/test/CodeGen/X86/stack-align2.ll (diff)
The file was modifiedllvm/lib/Target/X86/X86Subtarget.cpp (diff)
The file was modifiedcompiler-rt/test/ubsan/TestCases/TypeCheck/vptr.cpp (diff)
Commit c687af0c30b4dbdc9f614d5e061c888238e0f9c5 by david.spickett
[lldb] Don't send invalid region addresses to lldb server

Previously when <addr> in "memory region <addr>" didn't
parse correctly, we'd print an error then also ask lldb-server
for a region containing LLDB_INVALID_ADDRESS.

(lldb) memory region not_an_address
error: invalid address argument "not_an_address"...
error: Server returned invalid range

Only send the command to lldb-server if the address
parsed correctly.

(lldb) memory region not_an_address
error: invalid address argument "not_an_address"...

Reviewed By: labath

Differential Revision: https://reviews.llvm.org/D87694
The file was modifiedlldb/test/API/functionalities/memory-region/TestMemoryRegion.py (diff)
The file was modifiedlldb/source/Commands/CommandObjectMemory.cpp (diff)
Commit 9218f9283802b2d1ff33c490761fdb925b1e56d9 by cullen.rhodes
[clang][aarch64] ACLE: Support implicit casts between GNU and SVE vectors

This patch adds support for implicit casting between GNU vectors and SVE
vectors when `__ARM_FEATURE_SVE_BITS==N`, as defined by the Arm C
Language Extensions (ACLE, version 00bet5, section 3.7.3.3) for SVE [1].

This behavior makes it possible to use GNU vectors with ACLE functions
that operate on VLAT. For example:

  typedef int8_t vec __attribute__((vector_size(32)));
  vec f(vec x) { return svasrd_x(svptrue_b8(), x, 1); }

Tests are also added for implicit casting between GNU and fixed-length
SVE vectors created by the 'arm_sve_vector_bits' attribute. This
behavior makes it possible to use VLST with existing interfaces that
operate on GNUT. For example:

  typedef int8_t vec1 __attribute__((vector_size(32)));
  void f(vec1);
  #if __ARM_FEATURE_SVE_BITS==256 && __ARM_FEATURE_SVE_VECTOR_OPERATORS
  typedef svint8_t vec2 __attribute__((arm_sve_vector_bits(256)));
  void g(vec2 x) { f(x); } // OK
  #endif

The `__ARM_FEATURE_SVE_VECTOR_OPERATORS` feature macro indicates
interoperability with the GNU vector extension. This is the first patch
providing support for this feature, which once complete will be enabled
by the `-msve-vector-bits` flag, as the `__ARM_FEATURE_SVE_BITS` feature
currently is.

[1] https://developer.arm.com/documentation/100987/latest

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D87607
The file was modifiedclang/test/Sema/attr-arm-sve-vector-bits.c (diff)
The file was modifiedclang/lib/AST/ASTContext.cpp (diff)
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-cast.c (diff)
The file was modifiedclang/test/SemaCXX/attr-arm-sve-vector-bits.cpp (diff)
Commit 347d59b16c71194d7a9372dd69d3e41ebeca3113 by limo
[mlir][Linalg] Convolution tiling added to ConvOp vectorization pass

ConvOp vectorization supports now only convolutions of static shapes with dimensions
of size either 3(vectorized) or 1(not) as underlying vectors have to be of static
shape as well. In this commit we add support for convolutions of any size as well as
dynamic shapes by leveraging existing matmul infrastructure for tiling of both input
and kernel to sizes accepted by the previous version of ConvOp vectorization.
In the future this pass can be extended to take "tiling mask" as a user input which
will enable vectorization of user specified dimensions.

Differential Revision: https://reviews.llvm.org/D87676
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h (diff)
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-ndhwc-call.mlir (diff)
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-ncdhw-call.mlir (diff)
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-nhwc-call.mlir (diff)
The file was modifiedmlir/test/Conversion/LinalgToVector/linalg-to-vector.mlir (diff)
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-3d-call.mlir (diff)
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-nwc-call.mlir (diff)
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-call.mlir (diff)
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-ncw-call.mlir (diff)
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-1d-call.mlir (diff)
The file was modifiedmlir/test/lib/Transforms/TestConvVectorization.cpp (diff)
The file was modifiedmlir/integration_test/Dialect/Linalg/CPU/test-conv-2d-nchw-call.mlir (diff)
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp (diff)
Commit 4ae1bb193a596d5dab8e4e6acfcc081972b166a3 by llvm-dev
[AsmPrinter] Remove orphan DwarfUnit::shareAcrossDWOCUs declaration. NFCI.

Method implementation no longer exists.
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfUnit.h (diff)
Commit 8adf92e2d11ad23c946ae5bc10fc17505389e956 by llvm-dev
[AMDGPU] Remove orphan SITargetLowering::LowerINT_TO_FP declaration. NFCI.

Method implementation no longer exists.
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.h (diff)
Commit 550b1a6fd46f59134b2629ce23ca6a7874b45585 by llvm-dev
[AsmPrinter] DwarfDebug - use DebugLoc const references where possible. NFC.

Avoid unnecessary copies.
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (diff)
Commit f108e71437c47cc5172af4a7f704bb3f69d392f2 by vincentzhaorz
[MLIR] Turns swapId into a FlatAffineConstraints member func

`swapId` used to be a static function in `AffineStructures.cpp`. This diff makes it accessible from the external world by turning it into a member function of `FlatAffineConstraints`. This will be very helpful for other projects that need to manipulate the content of `FlatAffineConstraints`.

Differential Revision: https://reviews.llvm.org/D87766
The file was modifiedmlir/include/mlir/Analysis/AffineStructures.h (diff)
The file was modifiedmlir/lib/Analysis/AffineStructures.cpp (diff)
Commit 504697e6f40ecad3da44aa43568b869780644353 by thakis
[gn build] (manually) port c9af34027bc
The file was modifiedllvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn (diff)
Commit 68cfb02668550e3398c8ee8915732daf132f2652 by zinenko
[mlir] turn clang-format back on in C API test

C API test uses FileCheck comments inside C code and needs to
temporarily switch off clang-format to prevent it from messing with
FileCheck directives. A recently landed commit forgot to turn it back on
after a block of FileCheck comments. Fix that.
The file was modifiedmlir/test/CAPI/ir.c (diff)
Commit a615226743d0e986593961418efec76aedfa32b1 by david.green
[ARM] Extra fp16 bitcast tests. NFC
The file was modifiedllvm/test/CodeGen/ARM/fp16-bitcast.ll (diff)
Commit 71f237506b8fc06753eb733422d2fad20f622e2d by llvm-dev
DwarfFile.h - remove unnecessary includes. NFCI.

Use forward declarations where possible, move includes down to DwarfFile.cpp and avoid duplicate includes.
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfFile.h (diff)
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfFile.cpp (diff)
Commit 572e542c5e5fe2727502ab775a6b8c3d238c01b5 by llvm-dev
DwarfStringPool.cpp - remove unnecessary StringRef include. NFCI.

Already included in DwarfStringPool.h
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfStringPool.cpp (diff)
Commit fece1489d10bb189fe46bd08385ff6b8954dc39c by david.green
[ARM] Additional tests for qr intrinsics in loops. NFC
The file was addedllvm/test/CodeGen/Thumb2/mve-qrintr.ll
Commit c65627a1fe3be7521fc232d633bb6df577f55269 by david.spickett
Revert "[lldb] Don't send invalid region addresses to lldb server"

This reverts commit c687af0c30b4dbdc9f614d5e061c888238e0f9c5
due to a test failure on Windows.
The file was modifiedlldb/source/Commands/CommandObjectMemory.cpp (diff)
The file was modifiedlldb/test/API/functionalities/memory-region/TestMemoryRegion.py (diff)
Commit 97a476eb56726ef09bdd9c7f8c46d7e1c456d46b by sam.parker
[NFC][ARM] Tail fold test changes

Run update script on one test and add another.
The file was addedllvm/test/Transforms/LoopVectorize/ARM/tail-fold-multiple-icmps.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll (diff)
Commit ed53ff4cde331e0ffeb492dca6281aaeea2cd8cf by llvm-dev
SymbolizableObjectFile.h - remove unnecessary includes. NFCI.

Use forward declarations where possible, move includes down to SymbolizableObjectFile.cpp and avoid duplicate includes.
The file was modifiedllvm/lib/DebugInfo/Symbolize/SymbolizableObjectFile.cpp (diff)
The file was modifiedllvm/lib/DebugInfo/Symbolize/SymbolizableObjectFile.h (diff)
Commit abe0d8551da52ea1d0d8ad5f9ad71d22a7cd9928 by llvm-dev
MetadataLoader.cpp - remove unnecessary StringRef include. NFCI.

Already included in MetadataLoader.h
The file was modifiedllvm/lib/Bitcode/Reader/MetadataLoader.cpp (diff)
Commit 40e771c1c0d33c687230111271060c2ba761269f by mydeveloperday
[clang-format][regression][PR47461] ifdef causes catch to be seen as a function

https://bugs.llvm.org/show_bug.cgi?id=47461

The following change {D80940} caused a regression in code which ifdef's around the try and catch block cause incorrect brace placement around the catch

```
  try
  {
  }
  catch (...) {
    // This is not a small function
    bar = 1;
  }
}
```

The brace after the catch will be placed on a newline

Reviewed By: curdeius

Differential Revision: https://reviews.llvm.org/D87291
The file was modifiedclang/unittests/Format/FormatTest.cpp (diff)
The file was modifiedclang/lib/Format/FormatTokenLexer.cpp (diff)
Commit bb037c2a7625d9d13a86b18d9b8b0c75eb8c91cb by mikael.holmen
[ConstraintSystem] Remove local variable that is set but not read [NFC]

gcc 7.4 warns about it.
The file was modifiedllvm/lib/Analysis/ConstraintSystem.cpp (diff)
Commit aa896a0b3a9d93df818fbe9b68644ad90bcda831 by llvm-dev
Remove unnecessary forward declarations. NFCI.

All of these forward declarations are fully defined in headers that are directly included.
The file was modifiedllvm/include/llvm/Transforms/Utils/LoopVersioning.h (diff)
The file was modifiedllvm/include/llvm/Transforms/Utils/LoopUtils.h (diff)
The file was modifiedllvm/include/llvm/MC/MCParser/MCTargetAsmParser.h (diff)
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/CompileUtils.h (diff)
The file was modifiedllvm/include/llvm/DebugInfo/PDB/PDBSymbol.h (diff)
The file was modifiedllvm/include/llvm/ProfileData/SampleProf.h (diff)
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/GlobalMappingLayer.h (diff)
The file was modifiedllvm/include/llvm/MC/MCELFObjectWriter.h (diff)
The file was modifiedllvm/include/llvm/IR/LegacyPassManagers.h (diff)
Commit 788c7d2ec11dfc868a5b03478c922dc9699c6d47 by jrtc27
[clang][docs] Fix documentation of -O

D79916 changed the behaviour from -O2 to -O1 but the documentation was
not updated to reflect this.
The file was modifiedclang/docs/CommandGuide/clang.rst (diff)
Commit 03783f19dc78fc45fd987f892c314578b5e52d78 by spatel
[SLP] sort candidates to increase chance of optimal compare reduction

This is one (small) part of improving PR41312:
https://llvm.org/PR41312

As shown there and in the smaller tests here, if we have some member of the
reduction values that does not match the others, we want to push it to the
end (bring the matching members forward and together).

In the regression tests, we have 5 candidates for the 4 slots of the reduction.
If the one "wrong" compare is grouped with the others, it prevents forming the
ideal v4i1 compare reduction.

Differential Revision: https://reviews.llvm.org/D87772
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp (diff)
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll (diff)
Commit 0dca1ac617d802c0806f57f67eb830c4f5f3fffb by grimar
[llvm-readelf/obj][test] - Document what we print in various places for unnamed section symbols.

We have an issue with `ELFDumper<ELFT>::getSymbolSectionName`:
1) It is used deeply for both LLVM/GNU styles and might return LLVM-style only
   values to describe symbols: "Undefined", "Processor Specific", "Absolute", etc.

2) `getSymbolSectionName` is used by `getFullSymbolName` and these special values
   might appear in instead of symbol names in many places.
   This occurs for unnamed section symbols.

It was not noticed because for most cases I've found it is unexpected to have an
unnamed section symbol. This patch documents the existent behavior, adds tests and FIXMEs.

Differential revision: https://reviews.llvm.org/D87763
The file was modifiedllvm/test/tools/llvm-readobj/ELF/mips-plt.test (diff)
The file was modifiedllvm/test/tools/llvm-readobj/ELF/mips-got.test (diff)
The file was modifiedllvm/test/tools/llvm-readobj/ELF/symbol-shndx.test (diff)
The file was modifiedllvm/test/tools/llvm-readobj/ELF/hash-symbols.test (diff)
The file was modifiedllvm/test/tools/llvm-readobj/ELF/dyn-symbols.test (diff)
Commit 279943edf87887403fce72c505f9760764e416f0 by grimar
[obj2yaml] - Don't emit EM_NONE.

When ELF header's `e_machine == 0`, we emit:

```
Machine: EM_NONE
```

We can avoid doing this, because yaml2obj sets the
`e_machine` field to `EM_NONE` by default.

Differential revision: https://reviews.llvm.org/D87829
The file was modifiedllvm/test/tools/obj2yaml/ELF/emachine.yaml (diff)
The file was modifiedllvm/test/tools/obj2yaml/ELF/implicit-sections-order.yaml (diff)
The file was modifiedllvm/test/tools/obj2yaml/ELF/symbol-visibility.yaml (diff)
The file was modifiedllvm/test/tools/obj2yaml/ELF/gnu-unique-symbols.yaml (diff)
The file was modifiedllvm/test/tools/obj2yaml/ELF/versym-section.yaml (diff)
The file was modifiedllvm/test/tools/obj2yaml/ELF/invalid-section-name.yaml (diff)
The file was modifiedllvm/test/tools/obj2yaml/ELF/sht-symtab-shndx.yaml (diff)
The file was modifiedllvm/test/tools/obj2yaml/ELF/duplicate-symbol-and-section-names.yaml (diff)
The file was modifiedllvm/test/tools/obj2yaml/ELF/call-graph-profile-section.yaml (diff)
The file was modifiedllvm/test/tools/obj2yaml/ELF/null-section.yaml (diff)
The file was modifiedllvm/test/tools/obj2yaml/ELF/no-symtab.yaml (diff)
The file was modifiedllvm/test/tools/obj2yaml/ELF/stack-sizes.yaml (diff)
The file was modifiedllvm/tools/obj2yaml/elf2yaml.cpp (diff)
Commit f7185b271f5b3010c82a56417b437f2a44a79230 by kerry.mclaughlin
[SVE][CodeGen] Lower floating point -> integer conversions

This patch adds new ISD nodes, FCVTZS_MERGE_PASSTHRU &
FCVTZU_MERGE_PASSTHRU, which are used to lower scalable vector
FP_TO_SINT/FP_TO_UINT operations and the following intrinsics:
- llvm.aarch64.sve.fcvtzu
- llvm.aarch64.sve.fcvtzs

Reviewed By: efriedma, paulwalker-arm

Differential Revision: https://reviews.llvm.org/D87232
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td (diff)
The file was addedllvm/test/CodeGen/AArch64/sve-fcvt.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h (diff)
The file was addedllvm/test/CodeGen/AArch64/sve-split-fcvt.ll
Commit 9dc1e53787abbf4f2624c73272bf00e23fdffba0 by flo
[MemorySSA] Add another loop clobber test case.
The file was modifiedllvm/test/Analysis/MemorySSA/phi-translation.ll (diff)
Commit deb8f8bcf31540c657716ea5242183b0792702a1 by yvan.roux
[ARM][MachineOutliner] Add missing testcase for calls.
The file was addedllvm/test/CodeGen/ARM/machine-outliner-calls.mir
Commit f026812110878484d003f18660492e9321ef2df1 by llvm-dev
InstCombiner.h - remove unnecessary KnownBits.h include. NFCI.

Move the include down to cpp files with an implicit dependency.
The file was modifiedllvm/include/llvm/Transforms/InstCombine/InstCombiner.h (diff)
The file was modifiedllvm/lib/Target/X86/X86InstCombineIntrinsic.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp (diff)
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp (diff)
Commit e4a198eeee3ca96ff324d5b786e44c4915334054 by zhuoryin
[AMDGPU] Bump to ROCm 3.7 dependency hip_hcc->amdhip64

Differential Revision: https://reviews.llvm.org/D87773
The file was modifiedmlir/tools/mlir-rocm-runner/CMakeLists.txt (diff)
Commit 67ae46c820fa680e7f5828b4d8b94a562f51c9bf by llvm-dev
SafeStackLayout.cpp - remove unnecessary StackLifetime.h include. NFCI.

Already included in SafeStackLayout.h
The file was modifiedllvm/lib/CodeGen/SafeStackLayout.cpp (diff)
Commit 69516ddd028e8314f575a90bfca1724818fb5ca6 by n54
[compiler-rt] Avoid pulling libatomic to sanitizer tests

Avoid fallbacking to software emulated compiler atomics, that are usually
provided by libatomic, which is not always present.

This fixes the test on NetBSD, which does not provide libatomic in base.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D87568
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_atomic_test.cpp (diff)
Commit d566771779cd408bbe4985ea56e9b3c2ba247ed3 by llvm-dev
ValueList.cpp - remove unnecessary includes. NFCI.

Already included in ValueList.h
The file was modifiedllvm/lib/Bitcode/Reader/ValueList.cpp (diff)
Commit 46e59062a0e25be6e29d3fb342402f69b0e470b1 by llvm-dev
DwarfExpression.cpp - remove unnecessary includes. NFCI.

Already included in DwarfExpression.h
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp (diff)
Commit 85ba2f16633638e55ebc8e84bfbd0aaaa2f72b7a by llvm-dev
LiveDebugVariables.cpp - remove unnecessary Compiler.h include. NFCI.

Already included in LiveDebugVariables.h
The file was modifiedllvm/lib/CodeGen/LiveDebugVariables.cpp (diff)
Commit 85e578f53ad1ba21771470dc9516068a259d29cf by n54
[compiler-rt] Replace INLINE with inline

This fixes the clash with BSD headers.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D87562
The file was modifiedcompiler-rt/lib/msan/tests/msan_test.cpp (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator.h (diff)
The file was modifiedcompiler-rt/lib/scudo/scudo_tsd.h (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_checks.h (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_atomic_clang.h (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common.h (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_atomic.h (diff)
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.h (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_mac.h (diff)
The file was modifiedcompiler-rt/lib/scudo/scudo_allocator.cpp (diff)
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors.h (diff)
The file was modifiedcompiler-rt/lib/scudo/scudo_crc32.h (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_atomic_clang_x86.h (diff)
The file was modifiedcompiler-rt/lib/scudo/scudo_utils.h (diff)
The file was modifiedcompiler-rt/lib/asan/asan_report.cpp (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_atomic_msvc.h (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_atomic_clang_other.h (diff)
The file was modifiedcompiler-rt/lib/scudo/scudo_utils.cpp (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_atomic_clang_mips.h (diff)
The file was modifiedcompiler-rt/lib/asan/asan_malloc_local.h (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux.h (diff)
The file was modifiedcompiler-rt/lib/asan/asan_malloc_linux.cpp (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_secondary.h (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform_limits_freebsd.cpp (diff)
Commit 9339f68f21facc34fb0901045d571c818e1fa84a by n54
[compiler-rt] [tsan] [netbsd] Catch unsupported LONG_JMP_SP_ENV_SLOT

Error out during build for unsupported CPU.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D87602
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp (diff)
Commit 0efbb70b719e990fe153373eda5a604344ae36bb by Alexander Timofeev
[AMDGPU] should expand ROTL i16 to shifts.

Instruction combining pass turns library rotl implementation to llvm.fshl.i16.
In the selection dag the intrinsic is turned to ISD::ROTL node that cannot be selected.
Need to expand it to shifts again.

Reviewed By: rampitec, arsenm

Differential Revision: https://reviews.llvm.org/D87618
The file was modifiedllvm/test/CodeGen/AMDGPU/rotl.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/rotr.ll (diff)
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp (diff)
Commit 72c5feeed8d8d570e1c971ef069483491463a003 by n54
[compiler-rt] [netbsd] Include <sys/dkbad.h>

Fixes build on NetBSD/sparc64.
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform_limits_netbsd.cpp (diff)
Commit e7de267910e935ab885dae22b5191bfb118ca5f9 by n54
[compiler-rt] [hwasan] Replace INLINE with inline

Fixes the build after landing D87562.
The file was modifiedcompiler-rt/lib/hwasan/hwasan_malloc_bisect.h (diff)
Commit 5e0ded268929b87ddf2c5e077c9185554342f602 by herhut
[mlir][Standard] Canonicalize chains of tensor_cast operations

Adds a pattern that replaces a chain of two tensor_cast operations by a single tensor_cast operation if doing so will not remove constraints on the shapes.
The file was modifiedmlir/test/Transforms/canonicalize.mlir (diff)
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td (diff)
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp (diff)
Commit 7b2dd58eb09d3ead649bdd0a67f69d8776a636ff by n54
[compiler-rt] [scudo] Fix typo in function attribute

Fixes the build after landing https://reviews.llvm.org/D87562
The file was modifiedcompiler-rt/lib/scudo/scudo_allocator.cpp (diff)
Commit 34b27b9441d27ef886ea22b3bb75b357a5ec707b by david.green
[ARM] Sink splats to MVE intrinsics

The predicated MVE intrinsics are generated as, for example,
llvm.arm.mve.add.predicated(x, splat(y). p). We need to sink the splat
value back into the loop, like we do for other instructions, so we can
re-select qr variants.

Differential Revision: https://reviews.llvm.org/D87693
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-qrintr.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll (diff)
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp (diff)
Commit c3492a1aa1b98c8d81b0969d52cea7681f0624c2 by michael.hliao
[amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel.

- Need to lower COPY from SGPR to VGPR to a real instruction as the
  standard COPY is used where the source and destination are from the
  same register bank so that we potentially coalesc them together and
  save one COPY. Considering that, backend optimizations, such as CSE,
  won't handle them. However, the copy from SGPR to VGPR always needs
  materializing to a native instruction, it should be lowered into a
  real one before other backend optimizations.

Differential Revision: https://reviews.llvm.org/D87556
The file was modifiedllvm/test/CodeGen/AMDGPU/wqm.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll (diff)
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/fabs.ll (diff)
The file was addedllvm/test/CodeGen/AMDGPU/sgpr-copy-cse.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIFoldOperands.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/fneg-fabs.ll (diff)
Commit a3c28ccd49391931acd8b3b27dc98d7c606051e0 by Louis Dionne
[libc++] Remove some workarounds for missing variadic templates

We don't support GCC in C++03 mode, and Clang provides variadic templates
even in C++03 mode. So there's effectively no supported compiler that
doesn't support variadic templates.

This effectively gets rid of all uses of _LIBCPP_HAS_NO_VARIADICS, but
some workarounds for the lack of variadics remain.
The file was modifiedlibcxx/include/type_traits (diff)
The file was modifiedlibcxx/include/memory (diff)
The file was modifiedlibcxx/include/__config (diff)
The file was removedlibcxx/test/std/utilities/meta/meta.unary/meta.unary.cat/member_function_pointer_no_variadics.pass.cpp
The file was modifiedlibcxx/include/future (diff)
Commit 5b533d6cdeed21369dee4572b5485b1fd5d5dcf5 by xun
[Coroutine] Fix a bug where Coroutine incorrectly spills phi and invoke defs before CoroBegin

When a spill definition is before CoroBegin, we cannot spill it to the frame immediately after the definition. We have to spill it after the frame is ready.
The current implementation handles it properly for any other kinds of instructions except for PhINode and InvokeInst, which could also be defined before CoroBegin.
This patch fixes it by moving the CoroBegin dominance check earlier, so that it covers all cases.
Added a test.

Differential Revision: https://reviews.llvm.org/D87810
The file was modifiedllvm/lib/Transforms/Coroutines/CoroFrame.cpp (diff)
The file was addedllvm/test/Transforms/Coroutines/coro-spill-defs-before-corobegin.ll
Commit d5ce8233bfcfdeb66c715a1def8e0b34d236d48a by a.bataev
[OpenMP 5.0] Fix user-defined mapper privatization in tasks

This patch fixes the problem that user-defined mapper array is not correctly privatized inside a task. This problem causes openmp/libomptarget/test/offloading/target_depend_nowait.cpp fails.

Differential Revision: https://reviews.llvm.org/D84470
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntime.cpp (diff)
The file was modifiedclang/test/OpenMP/target_depend_codegen.cpp (diff)
Commit 559f9198125392bfa8e7d462aa8e87fcf5030185 by mascasa
[DFSan] Add bcmp wrapper.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D87801
The file was modifiedcompiler-rt/test/dfsan/custom.cpp (diff)
The file was modifiedcompiler-rt/lib/dfsan/dfsan_custom.cpp (diff)
The file was modifiedcompiler-rt/lib/dfsan/done_abilist.txt (diff)
Commit 3ee87a976d52a2379d007046f9a1ad4a07f440c0 by Sanne.Wouda
Precommit test updates
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-fadd.ll (diff)
The file was addedllvm/test/CodeGen/AArch64/faddp.ll
The file was addedllvm/test/CodeGen/AArch64/faddp-half.ll
Commit d5fd3d9b903ef6d96c6b3b82434dd0461faaba55 by Sanne.Wouda
[AArch64] Match pairwise add/fadd pattern

D75689 turns the faddp pattern into a shuffle with vector add.

Match this new pattern in target-specific DAG combine, rather than ISel,
because legalization (for v2f32) turns it into a bit of a mess.

- extended to cover f16, f32, f64 and i64
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/faddp-half.ll (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td (diff)
The file was modifiedllvm/test/CodeGen/AArch64/faddp.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-fadd.ll (diff)
Commit 40df06cdafc010002fc9cfe1dda73d689b7d27a6 by Yaxun.Liu
[CUDA][HIP] Defer overloading resolution diagnostics for host device functions

In CUDA/HIP a function may become implicit host device function by
pragma or constexpr. A host device function is checked in both
host and device compilation. However it may be emitted only
on host or device side, therefore the diagnostics should be
deferred until it is known to be emitted.

Currently clang is only able to defer certain diagnostics. This causes
false alarms and limits the usefulness of host device functions.

This patch lets clang defer all overloading resolution diagnostics for host device functions.

An option -fgpu-defer-diag is added to control this behavior. By default
it is off.

It is NFC for other languages.

Differential Revision: https://reviews.llvm.org/D84364
The file was modifiedclang/include/clang/Basic/DiagnosticSerialization.h (diff)
The file was modifiedclang/lib/Sema/SemaTemplateInstantiate.cpp (diff)
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp (diff)
The file was modifiedclang/lib/Driver/ToolChains/HIP.cpp (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticSema.h (diff)
The file was modifiedclang/include/clang/Sema/Sema.h (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td (diff)
The file was addedclang/test/SemaCUDA/deferred-oeverload.cu
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp (diff)
The file was modifiedclang/lib/Sema/SemaDecl.cpp (diff)
The file was modifiedclang/include/clang/Driver/Options.td (diff)
The file was modifiedclang/lib/Sema/SemaStmtAsm.cpp (diff)
The file was modifiedclang/lib/Sema/SemaExprObjC.cpp (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticComment.h (diff)
The file was modifiedclang/lib/Sema/AnalysisBasedWarnings.cpp (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticRefactoring.h (diff)
The file was modifiedclang/include/clang/Basic/LangOptions.def (diff)
The file was modifiedclang/include/clang/Basic/Diagnostic.td (diff)
The file was addedclang/test/TableGen/deferred-diag.td
The file was modifiedclang/include/clang/Basic/DiagnosticCrossTU.h (diff)
The file was modifiedclang/test/TableGen/DiagnosticBase.inc (diff)
The file was modifiedclang/lib/Sema/SemaSYCL.cpp (diff)
The file was modifiedclang/lib/Sema/SemaType.cpp (diff)
The file was modifiedclang/lib/Basic/DiagnosticIDs.cpp (diff)
The file was modifiedclang/lib/Sema/SemaOverload.cpp (diff)
The file was modifiedclang/lib/Sema/SemaTemplateVariadic.cpp (diff)
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticDriver.h (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticFrontend.h (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticIDs.h (diff)
The file was modifiedclang/lib/Sema/Sema.cpp (diff)
The file was modifiedclang/tools/diagtool/DiagnosticNames.cpp (diff)
The file was modifiedclang/lib/Sema/SemaAttr.cpp (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticAnalysis.h (diff)
The file was modifiedclang/lib/Driver/ToolChains/Cuda.cpp (diff)
The file was modifiedclang/utils/TableGen/ClangDiagnosticsEmitter.cpp (diff)
The file was modifiedclang/lib/Sema/SemaCUDA.cpp (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticAST.h (diff)
The file was modifiedclang/lib/Sema/SemaStmt.cpp (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticParse.h (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticLex.h (diff)
Commit 72a4a478fe12f3052d1f73c5e5b4a905c8dfcf1b by david.green
[ARM] Add more MVE postinc distribution tests. NFC
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir (diff)
Commit 6d3cabd90eedee07a6e6cbf2dfa952e23cef192c by clementval
[mlir][openacc] Change operand type from index to AnyInteger in parallel op

This patch change the type of operands async, wait, numGangs, numWorkers and vectorLength from index
to AnyInteger to fit with acc.loop and the OpenACC specification.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D87712
The file was modifiedmlir/include/mlir/Dialect/OpenACC/OpenACCOps.td (diff)
The file was modifiedmlir/test/Dialect/OpenACC/ops.mlir (diff)
The file was modifiedmlir/lib/Dialect/OpenACC/IR/OpenACC.cpp (diff)
Commit f0e028f4b32393676b5d3eb36d6598ec5a390180 by clementval
[flang][openacc] Lower clauses on loop construct to OpenACC dialect

Lower OpenACCLoopConstruct and most of the clauses to the OpenACC acc.loop operation in MLIR.
This patch refelcts what can be upstream from PR flang-compiler/f18-llvm-project#419

Reviewed By: SouraVX

Differential Revision: https://reviews.llvm.org/D87389
The file was modifiedflang/lib/Lower/OpenACC.cpp (diff)
The file was modifiedflang/include/flang/Optimizer/Dialect/FIRDialect.h (diff)
Commit 7688027f166311164982bb15fe44041f31b6d45f by mkazantsev
[Test] Add tests showing that IndVars cannot prove (X + 1 > X)
The file was addedllvm/test/Transforms/IndVarSimplify/trivial-checks.ll
Commit df017fd906bba81af38749fe374ae2635fd51389 by mascasa
Revert "[DFSan] Add bcmp wrapper."

This reverts commit 559f9198125392bfa8e7d462aa8e87fcf5030185 due to bot
failure.
The file was modifiedcompiler-rt/lib/dfsan/dfsan_custom.cpp (diff)
The file was modifiedcompiler-rt/lib/dfsan/done_abilist.txt (diff)
The file was modifiedcompiler-rt/test/dfsan/custom.cpp (diff)
Commit 2a56a0ba086491e51c54026c6badae6496539487 by llvm-dev
ModuloSchedule.cpp - remove unnecessary includes. NFCI.

Already included in ModuloSchedule.h
The file was modifiedllvm/lib/CodeGen/ModuloSchedule.cpp (diff)
Commit 7f1f89ec8d9944559042bb6d3b1132eabe3409de by Yaxun.Liu
Fix build failure in clangd
The file was modifiedclang-tools-extra/clangd/Diagnostics.cpp (diff)
Commit f16abe5f84eee8db18d5eb5a21ab543146626ea6 by hanchung
[mlir][Vector] Add a folder for vector.broadcast

Fold the operation if the source is a scalar constant or splat constant.

Update transform-patterns-matmul-to-vector.mlir because the broadcast ops are folded in the conversion.

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D87703
The file was modifiedmlir/test/Dialect/Vector/canonicalize.mlir (diff)
The file was modifiedmlir/test/Dialect/Linalg/transform-patterns-matmul-to-vector.mlir (diff)
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td (diff)
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp (diff)
Commit 79b21fc187643416dbd21db10abe46a91b4c3f09 by Amara Emerson
[AArch64][GlobalISel] Fix bug in fewVectorElts action while legalizing oversize G_FPTRUNC vectors.

For <8 x s32> = fptrunc <8 x s64> the fewerElementsVector action tries to break
down the source vector into the final source vectors of <2 x s64> using unmerge.
This fixes a crash due to using the wrong number of elements for the breakdown
type.

Also add some legalizer tests for explicitly G_FPTRUNC which we didn't have.

Differential Revision: https://reviews.llvm.org/D87814
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp (diff)
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vcvt.ll (diff)
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir
Commit 7f7993e0daf459c308747f034e3fbd73889c7ab3 by david.green
[ARM] Expand distributing increments to also handle existing pre/post inc instructions.

This extends the distributing postinc code in load/store optimizer to
also handle the case where there is an existing pre/post inc instruction,
where subsequent instructions can be modified to use the adjusted
offset from the increment. This can save us having to keep the old
register live past the increment instruction.

Differential Revision: https://reviews.llvm.org/D83377
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vst3.ll (diff)
The file was modifiedllvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vst2.ll (diff)
Commit c6ebe3fd002c1d3b903ab6e912ebd815fdb0e964 by spatel
[InstSimplify] add tests for FP constant miscompile; NFC (PR43907)
The file was modifiedllvm/test/Transforms/InstSimplify/ConstProp/cast.ll (diff)
Commit 7d593d0d6905b55ca1124fca5e4d1ebb17203138 by benny.kra
[amdgpu] Compilation fix for Release

Reviewed By: bkramer

Differential Revision: https://reviews.llvm.org/D87838
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp (diff)
Commit 1e19165bd89db6671a80e0b25b32d5c7ae79455c by ecaldas
[SyntaxTree][Synthesis] Fix allocation in `createTree` for more general use

Prior to this change `createTree` could not create arbitrary syntax
trees. Now it dispatches to the constructor of the concrete syntax tree
according to the `NodeKind` passed as argument. This allows reuse inside
the Synthesis API.  # Please enter the commit message for your changes.
Lines starting

Differential Revision: https://reviews.llvm.org/D87820
The file was modifiedclang/lib/Tooling/Syntax/Synthesis.cpp (diff)
The file was modifiedclang/include/clang/Tooling/Syntax/BuildTree.h (diff)
Commit 50dd545b00ed72a9ed2031cb5eb9bf26dd5af0c0 by mascasa
[DFSan] Add bcmp wrapper.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D87801
The file was modifiedcompiler-rt/lib/dfsan/dfsan_custom.cpp (diff)
The file was modifiedcompiler-rt/test/dfsan/custom.cpp (diff)
The file was modifiedcompiler-rt/lib/dfsan/done_abilist.txt (diff)
Commit e09107ab80dced55414fa458cf78e6cdfe90da6e by raul.tambre
[Sema] Introduce BuiltinAttr, per-declaration builtin-ness

Instead of relying on whether a certain identifier is a builtin, introduce BuiltinAttr to specify a declaration as having builtin semantics.

This fixes incompatible redeclarations of builtins, as reverting the identifier as being builtin due to one incompatible redeclaration would have broken rest of the builtin calls.
Mostly-compatible redeclarations of builtins also no longer have builtin semantics. They don't call the builtin nor inherit their attributes.
A long-standing FIXME regarding builtins inside a namespace enclosed in extern "C" not being recognized is also addressed.

Due to the more correct handling attributes for builtin functions are added in more places, resulting in more useful warnings.
Tests are updated to reflect that.

Intrinsics without an inline definition in intrin.h had `inline` and `static` removed as they had no effect and caused them to no longer be recognized as builtins otherwise.

A pthread_create() related test is XFAIL-ed, as it relied on it being recognized as a builtin based on its name.
The builtin declaration syntax is too restrictive and doesn't allow custom structs, function pointers, etc.
It seems to be the only case and fixing this would require reworking the current builtin syntax, so this seems acceptable.

Fixes PR45410.

Reviewed By: rsmith, yutsumi

Differential Revision: https://reviews.llvm.org/D77491
The file was modifiedclang/test/CodeGenCXX/builtins.cpp (diff)
The file was modifiedclang/include/clang/Basic/Attr.td (diff)
The file was modifiedclang/lib/Serialization/ASTReader.cpp (diff)
The file was modifiedclang/test/AST/ast-dump-attr.cpp (diff)
The file was modifiedclang/test/SemaCXX/cxx11-compat.cpp (diff)
The file was modifiedclang/test/SemaCXX/warn-unused-local-typedef.cpp (diff)
The file was modifiedclang/test/Sema/implicit-builtin-decl.c (diff)
The file was modifiedclang/lib/AST/Decl.cpp (diff)
The file was modifiedclang/include/clang/Basic/Builtins.def (diff)
The file was addedclang/test/CodeGen/builtin-redeclaration.c
The file was modifiedclang/test/CodeGen/callback_pthread_create.c (diff)
The file was modifiedclang/include/clang/Sema/Sema.h (diff)
The file was modifiedclang/lib/Sema/SemaExpr.cpp (diff)
The file was modifiedclang/lib/Serialization/ASTWriter.cpp (diff)
The file was modifiedclang/include/clang/Basic/IdentifierTable.h (diff)
The file was modifiedclang/test/Sema/warn-fortify-source.c (diff)
The file was modifiedclang/lib/Sema/SemaDecl.cpp (diff)
The file was modifiedclang/lib/Headers/intrin.h (diff)
The file was modifiedclang/lib/Sema/SemaLookup.cpp (diff)
Commit fb182028361504569ff6322bfa12b12e1ab74e30 by zhuoryin
[AMDGPU] Fix ROCm unit test memref initialization
The file was modifiedmlir/tools/mlir-rocm-runner/mlir-rocm-runner.cpp (diff)
The file was modifiedmlir/test/mlir-rocm-runner/vector-transferops.mlir (diff)
The file was modifiedmlir/test/mlir-rocm-runner/vecadd.mlir (diff)
The file was modifiedllvm/include/llvm/Transforms/InstCombine/InstCombiner.h (diff)
Commit 50f1d4517ae46a43b9bd1b488cc632b65de0dbbe by Jinsong Ji
[PowerPC][AIX] Don't hardcode python invoke command line

We shouldn't assume python exists, we should let lit
to decide whether it is python or python3 and expand the path.
The file was modifiedllvm/test/CodeGen/PowerPC/aix-overflow-toc.py (diff)
Commit e06914b59bf8e2344969def6f20b394cacce186b by spatel
[VectorCombine] add test for multi-use load (PR47558); NFC
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load.ll (diff)
Commit ddd9575d15ad8f0fa746b5ece63530c4619e3e9c by spatel
[VectorCombine] rearrange bailouts for load insert for efficiency; NFC
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp (diff)
Commit 772bd8a7d99b8db899f594d393986e4b6cd85aa1 by Yaxun.Liu
Revert "[CUDA][HIP] Defer overloading resolution diagnostics for host device functions"

This reverts commit 7f1f89ec8d9944559042bb6d3b1132eabe3409de.

This reverts commit 40df06cdafc010002fc9cfe1dda73d689b7d27a6.
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td (diff)
The file was modifiedclang/include/clang/Basic/Diagnostic.td (diff)
The file was modifiedclang/lib/Sema/SemaSYCL.cpp (diff)
The file was modifiedclang/lib/Sema/AnalysisBasedWarnings.cpp (diff)
The file was modifiedclang/include/clang/Sema/Sema.h (diff)
The file was modifiedclang/lib/Sema/SemaTemplateInstantiate.cpp (diff)
The file was modifiedclang/lib/Sema/SemaCUDA.cpp (diff)
The file was modifiedclang/lib/Sema/SemaExprObjC.cpp (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticAST.h (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticParse.h (diff)
The file was modifiedclang/include/clang/Driver/Options.td (diff)
The file was modifiedclang/lib/Sema/SemaOverload.cpp (diff)
The file was modifiedclang/utils/TableGen/ClangDiagnosticsEmitter.cpp (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticCrossTU.h (diff)
The file was modifiedclang/include/clang/Basic/LangOptions.def (diff)
The file was modifiedclang-tools-extra/clangd/Diagnostics.cpp (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticSema.h (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticSerialization.h (diff)
The file was removedclang/test/SemaCUDA/deferred-oeverload.cu
The file was modifiedclang/lib/Sema/SemaTemplateVariadic.cpp (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticComment.h (diff)
The file was modifiedclang/lib/Driver/ToolChains/Cuda.cpp (diff)
The file was modifiedclang/tools/diagtool/DiagnosticNames.cpp (diff)
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp (diff)
The file was removedclang/test/TableGen/deferred-diag.td
The file was modifiedclang/lib/Driver/ToolChains/HIP.cpp (diff)
The file was modifiedclang/lib/Sema/SemaStmt.cpp (diff)
The file was modifiedclang/lib/Sema/SemaDecl.cpp (diff)
The file was modifiedclang/lib/Sema/SemaStmtAsm.cpp (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticDriver.h (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticIDs.h (diff)
The file was modifiedclang/lib/Basic/DiagnosticIDs.cpp (diff)
The file was modifiedclang/lib/Sema/SemaType.cpp (diff)
The file was modifiedclang/test/TableGen/DiagnosticBase.inc (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticAnalysis.h (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticLex.h (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticRefactoring.h (diff)
The file was modifiedclang/include/clang/Basic/DiagnosticFrontend.h (diff)
The file was modifiedclang/lib/Sema/Sema.cpp (diff)
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp (diff)
The file was modifiedclang/lib/Sema/SemaAttr.cpp (diff)
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp (diff)
Commit 829d14ee0a6aa79c89f7f3d9fcd9d27d3efd2b91 by Yaxun.Liu
Revert "[NFC] Refactor DiagnosticBuilder and PartialDiagnostic"

This reverts commit ee5519d323571c4a9a7d92cb817023c9b95334cd.
The file was modifiedclang/include/clang/AST/DeclCXX.h (diff)
The file was modifiedclang/include/clang/Sema/ParsedAttr.h (diff)
The file was modifiedclang/lib/Basic/Diagnostic.cpp (diff)
The file was modifiedclang/include/clang/AST/TemplateName.h (diff)
The file was modifiedclang/include/clang/Basic/PartialDiagnostic.h (diff)
The file was modifiedclang/include/clang/AST/Attr.h (diff)
The file was modifiedclang/include/clang/AST/CanonicalType.h (diff)
The file was modifiedclang/include/clang/AST/TemplateBase.h (diff)
The file was modifiedclang/include/clang/Basic/Diagnostic.h (diff)
The file was modifiedclang/include/clang/AST/NestedNameSpecifier.h (diff)
The file was modifiedclang/lib/AST/TemplateBase.cpp (diff)
The file was modifiedclang/lib/AST/TemplateName.cpp (diff)
The file was modifiedclang/include/clang/AST/Decl.h (diff)
The file was modifiedclang/lib/AST/DeclCXX.cpp (diff)
The file was modifiedclang/lib/AST/ASTContext.cpp (diff)
The file was modifiedclang/include/clang/AST/DeclarationName.h (diff)
The file was modifiedclang/include/clang/AST/ASTContext.h (diff)
The file was modifiedclang/include/clang/Sema/Ownership.h (diff)
The file was modifiedclang/include/clang/AST/Type.h (diff)
The file was modifiedclang/include/clang/Sema/Sema.h (diff)
Commit 296e97ae8f7183c2f8737b9e6e68df4904dbfadf by uday
[MLIR] Support for return values in Affine.For yield

Add support for return values in affine.for yield along the same lines
as scf.for and affine.parallel.

Signed-off-by: Abhishek Varma <abhishek.varma@polymagelabs.com>

Differential Revision: https://reviews.llvm.org/D87437
The file was modifiedmlir/lib/Dialect/Affine/IR/AffineOps.cpp (diff)
The file was modifiedmlir/include/mlir/Dialect/Affine/EDSC/Builders.h (diff)
The file was modifiedmlir/include/mlir/Dialect/Affine/IR/AffineOps.td (diff)
The file was modifiedmlir/test/EDSC/builder-api-test.cpp (diff)
The file was modifiedmlir/test/Dialect/Affine/invalid.mlir (diff)
The file was modifiedmlir/test/Dialect/Affine/ops.mlir (diff)
The file was modifiedmlir/lib/Dialect/Affine/EDSC/Builders.cpp (diff)
Commit 0602e8f77f8662c85155b8cf02937a2e71c01e12 by uday
[MLIR][Affine] Add parametric tile size support for affine.for tiling

Add support to tile affine.for ops with parametric sizes (i.e., SSA
values). Currently supports hyper-rectangular loop nests with constant
lower bounds only. Move methods

  - moveLoopBody(*)
  - getTileableBands(*)
  - checkTilingLegality(*)
  - tilePerfectlyNested(*)
  - constructTiledIndexSetHyperRect(*)

to allow reuse with constant tile size API. Add a test pass -test-affine
-parametric-tile to test parametric tiling.

Differential Revision: https://reviews.llvm.org/D87353
The file was modifiedmlir/lib/Transforms/Utils/LoopUtils.cpp (diff)
The file was modifiedmlir/test/lib/Transforms/CMakeLists.txt (diff)
The file was addedmlir/test/Dialect/Affine/loop-tiling-parametric.mlir
The file was addedmlir/test/lib/Transforms/TestAffineLoopParametricTiling.cpp
The file was modifiedmlir/tools/mlir-opt/mlir-opt.cpp (diff)
The file was modifiedmlir/include/mlir/Transforms/LoopUtils.h (diff)
The file was modifiedmlir/lib/Dialect/Affine/Transforms/LoopTiling.cpp (diff)
Commit 3783d3bc7b3dd966ac3b9436b73f16f855d12ff2 by craig.topper
[X86] Don't match x87 register inline asm constraints unless the VT is floating point or its a clobber

The register class picked will be the RFP80 register class which has a f80 VT. The code in SelectionDAGBuilder that generates copies around inline assembly doesn't know how to handle an integer and floating point type of different bit widths.

The test case is derived from this https://godbolt.org/z/sEa659 which gcc accepts but clang crashes on. This patch just gives a more graceful error. I'm not sure if the single element struct case is special in gcc. Adding another field to the struct makes gcc reject it. If we want to support this correctly I think we need a change in the frontend to give us the true element type. Right now the frontend just realizes the constraint can take a memory argument so creates an integer type of the same size and bitcasts.

Differential Revision: https://reviews.llvm.org/D87485
The file was addedllvm/test/CodeGen/X86/asm-reject-x87-int.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp (diff)
Commit 48a23bccf3732e1480ad169bd4a08a68bb100bfa by spatel
[VectorCombine] limit load+insert transform to one-use

As discussed in:
https://llvm.org/PR47558
...there are several potential fixes/follow-ups visible
in the test case, but this is the quickest and safest
fix of the perf regression.
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load.ll (diff)
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp (diff)
Commit bea7749d0364a8c694f236a97d58167a33efdb9e by Amara Emerson
[AArch64][GlobalISel] Make <8 x s16> and <16 x s8> legal for shifts.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir (diff)
Commit 7d5b10348371644c69041965b9864886e9961ddd by Amara Emerson
[AArch64][GlobalISel] Widen G_EXTRACT_VECTOR_ELT element types if < 8b.

In order to not unnecessarily promote the source vector to greater than our
native vector size of 128b, I've added some cascading rules to widen based on
the number of elements.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir (diff)
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir (diff)
Commit 1e5b7e91aa64c267e495cb4bd8351b1840694437 by rnk
[PDB] Split TypeServerSource and extend type index map lifetime

Extending the lifetime of these type index mappings does increase memory
usage (+2% in my case), but it decouples type merging from symbol
merging. This is a pre-requisite for two changes that I have in mind:
- parallel type merging: speeds up slow type merging
- defered symbol merging: avoid heap allocating (relocating) all symbols

This eliminates CVIndexMap and moves its data into TpiSource. The maps
are also split into a SmallVector and ArrayRef component, so that the
ipiMap can alias the tpiMap for /Z7 object files, and so that both maps
can simply alias the PDB type server maps for /Zi files.

Splitting TypeServerSource establishes that all input types to be merged
can be identified with two 32-bit indices:
- The index of the TpiSource object
- The type index of the record
This is useful, because this information can be stored in a single
64-bit atomic word to enable concurrent hashtable insertion.

One last change is that now all object files with debugChunks get a
TpiSource, even if they have no type info. This avoids some null checks
and special cases.

Differential Revision: https://reviews.llvm.org/D87736
The file was modifiedlld/COFF/InputFiles.cpp (diff)
The file was modifiedlld/COFF/PDB.cpp (diff)
The file was modifiedlld/COFF/DebugTypes.h (diff)
The file was modifiedlld/COFF/TypeMerger.h (diff)
The file was modifiedlld/COFF/DebugTypes.cpp (diff)
Commit a35c7f30769b4bc3745796af58c932f303a014e1 by mcinally
[SVE][WIP] Implement lowering for fixed length VSELECT to Scalable

Map fixed length VSELECT to its Scalable equivalent.

Differential Revision: https://reviews.llvm.org/D85364
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp (diff)
The file was addedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
The file was addedllvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h (diff)
Commit 7e4c6fb854660318dc31ecb9842f6cfebb18c8e0 by andrew_litteken
[IRSim] Adding IR Instruction Mapper

This introduces the IRInstructionMapper, and the associated wrapper for
instructions, IRInstructionData, that maps IR level Instructions to
unsigned integers.

Mapping is done mainly by using the "isSameOperationAs" comparison
between two instructions.  If they return true, the opcode, result type,
and operand types of the instruction are used to hash the instruction
with an unsigned integer.  The mapper accepts instruction ranges, and
adds each resulting integer to a list, and each wrapped instruction to
a separate list.

At present, branches, phi nodes are not mapping and exception handling
is illegal.  Debug instructions are not considered.

The different mapping schemes are tested in
unittests/Analysis/IRSimilarityIdentifierTest.cpp

Recommit of: b04c1a9d3127730c05e8a22a0e931a12a39528df

Differential Revision: https://reviews.llvm.org/D86968
The file was addedllvm/include/llvm/Analysis/IRSimilarityIdentifier.h
The file was addedllvm/lib/Analysis/IRSimilarityIdentifier.cpp
The file was addedllvm/unittests/Analysis/IRSimilarityIdentifierTest.cpp
The file was modifiedllvm/lib/Analysis/CMakeLists.txt (diff)
The file was modifiedllvm/unittests/Analysis/CMakeLists.txt (diff)
Commit 667762c64e0b2925112037c197709402b4f2221d by llvmgnsyncbot
[gn build] Port 7e4c6fb8546
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Analysis/BUILD.gn (diff)
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/Analysis/BUILD.gn (diff)
Commit c145a1ca2593e3b8b79687d5ba8c3230c41b5130 by jonathan_roelofs
AArch64::ArchKind's underlying type is uint64_t
The file was modifiedllvm/include/llvm/Support/AArch64TargetParser.h (diff)
The file was modifiedllvm/lib/Support/AArch64TargetParser.cpp (diff)
The file was modifiedllvm/unittests/Support/TargetParserTest.cpp (diff)
The file was modifiedclang/lib/Driver/ToolChains/Arch/AArch64.cpp (diff)
Commit 5813fca1076089c835de737834955a0fe7eb3898 by Vitaly Buka
[Lsan] Use fp registers to search for pointers

X86 can use xmm registers for pointers operations. e.g. for std::swap.
I don't know yet if it's possible on other platforms.

NT_X86_XSTATE includes all registers from NT_FPREGSET so
the latter used only if the former is not available. I am not sure how
reasonable to expect that but LLD has such fallback in
NativeRegisterContextLinux_x86_64::ReadFPR.

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D87754
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp (diff)
The file was modifiedcompiler-rt/test/lsan/TestCases/use_registers.cpp (diff)
The file was addedcompiler-rt/test/lsan/TestCases/use_registers_extra.cpp
Commit a4bb71b1c0d9952208ad32bc4992cc211d43c5bb by wei.huang
Disable hoisting MI to hotter basic blocks when using pgo

This is a follow up patch for https://reviews.llvm.org/D63676 to
enable the feature when using pgo.

Differential Revision: https://reviews.llvm.org/D85240
The file was modifiedllvm/test/CodeGen/X86/opt-pipeline.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/O3-pipeline.ll (diff)
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll (diff)
The file was modifiedllvm/lib/CodeGen/MachineLICM.cpp (diff)
Commit 51973a607dfa4681037aff43e295f3ea1fb0f3f4 by flo
[SCEV] Add test cases for max BTC with loop guard info.

This adds test cases for PR40961 and PR47247. They illustrate cases in
which the max backedge-taken count can be improved by information from
the loop guards.
The file was addedllvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
Commit 59855b9d3bacc4321e3dd22ccf09bd9d177fdb6f by nikita.ppv
[GVN] Add additional assume tests (NFC)

The other assume tests seem to be dealing with equalities in
particular. Test implication for the condition itself, especially
the negated case from PR47496.
The file was addedllvm/test/Transforms/GVN/assume.ll
Commit 91ce8e121b7f24ef68fad0ab07f6ab7e1ee06855 by nikita.ppv
[GVN] Use that assume(!X) implies X==false (PR47496)

We already use that assume(X) implies X==true, do the same for
assume(!X) implying X==false. This fixes PR47496.
The file was modifiedllvm/lib/Transforms/Scalar/GVN.cpp (diff)
The file was modifiedllvm/test/Transforms/GVN/assume.ll (diff)
Commit 1cee33e9dbb6c30ff1dd30453a263696bfccfd8a by whitneyt
[LoopUnrollAndJam] Allow unroll and jam loops forced by user.

Summary: Allow unroll and jam loops forced by user.
LoopUnrollAndJamPass is still disabled by default in the NPM pipeline,
and can be controlled by -enable-npm-unroll-and-jam.

Reviewed By: Meinersbur, dmgreen

Differential Revision: https://reviews.llvm.org/D87786
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp (diff)
The file was modifiedllvm/test/Transforms/LoopUnrollAndJam/pragma-explicit.ll (diff)
Commit 05d4c4ebc2fb006b8a2bd05b24c6aba10dd2eef8 by nikita.ppv
[InstCombine] Canonicalize SPF_ABS to abs intrinc

Enable canonicalization of SPF_ABS and SPF_NABS to the abs intrinsic.

To be conservative, the one-use check on the comparison is retained,
this may be relaxed if all goes well.

It's pretty likely that this will uncover places that missing
handling for the abs() intrinsic. Please report any seen performance
regressions.

Differential Revision: https://reviews.llvm.org/D87188
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll (diff)
The file was modifiedllvm/test/Transforms/InstCombine/select_meta.ll (diff)
The file was modifiedllvm/test/Transforms/InstCombine/call-callconv.ll (diff)
The file was modifiedllvm/test/Transforms/InstCombine/abs_abs.ll (diff)
The file was modifiedllvm/test/Transforms/InstCombine/abs-1.ll (diff)
The file was modifiedllvm/test/Transforms/InstCombine/sub-of-negatible.ll (diff)
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp (diff)
The file was modifiedclang/test/CodeGen/builtins-wasm.c (diff)
The file was modifiedllvm/test/Transforms/InstCombine/max-of-nots.ll (diff)
The file was modifiedllvm/test/Transforms/PhaseOrdering/min-max-abs-cse.ll (diff)
The file was modifiedllvm/test/Transforms/InstCombine/cttz-abs.ll (diff)
The file was modifiedllvm/test/Transforms/InstCombine/icmp.ll (diff)
Commit 53ba045f488f7ef7d4894926fad8de0b76f1e20a by alexshap
[llvm-install-name-tool] Update the command-line guide
The file was modifiedllvm/docs/CommandGuide/llvm-install-name-tool.rst (diff)
Commit 179a22e807a40ae5821920cec3c1933eef4dc30c by aeubanks
[NewPM] Fix pr45927.ll under NPM
The file was modifiedllvm/test/Analysis/MemorySSA/pr45927.ll (diff)
Commit a0017c2bc258690146f18491317144e487ddb101 by flo
[MemorySSA] Be more conservative when traversing MemoryPhis.

I think we need to be even more conservative when traversing memory
phis, to make sure we catch any loop carried dependences.

This approach updates fillInCurrentPair to use unknown sizes for
locations when we walk over a phi, unless the location is guaranteed to
be loop-invariant for any possible loop. Using an unknown size for
locations should ensure we catch all memory accesses to locations after
the given memory location, which includes loop-carried dependences.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D87778
The file was modifiedllvm/test/Analysis/MemorySSA/phi-translation.ll (diff)
The file was modifiedllvm/include/llvm/Analysis/MemorySSA.h (diff)
Commit 0ff28fa6a75617d61b1aeea77463d6a1684c3c89 by dschuff
Support dwarf fission for wasm object files

Initial support for dwarf fission sections (-gsplit-dwarf) on wasm.
The most interesting change is support for writing 2 files (.o and .dwo) in the
wasm object writer. My approach moves object-writing logic into its own function
and calls it twice, swapping out the endian::Writer (W) in between calls.
It also splits the import-preparation step into its own function (and skips it when writing a dwo).

Differential Revision: https://reviews.llvm.org/D85685
The file was modifiedllvm/lib/MC/MCAsmBackend.cpp (diff)
The file was modifiedllvm/lib/MC/MCObjectFileInfo.cpp (diff)
The file was modifiedllvm/lib/MC/WasmObjectWriter.cpp (diff)
The file was addedllvm/test/DebugInfo/WebAssembly/fission-cu.ll
The file was modifiedllvm/include/llvm/MC/MCWasmObjectWriter.h (diff)
The file was addedllvm/test/DebugInfo/WebAssembly/fission-sections.ll
The file was modifiedclang/test/Driver/split-debug.c (diff)
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp (diff)
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (diff)
Commit 99e865b618f31c69776273a60addbd88917a29d9 by qcolombet
[TargetRegisterInfo] Add a couple of target hooks for the greedy register allocator

Before this patch, the last chance recoloring and deferred spilling
techniques were solely controled by command line options.
This patch adds target hooks for these two techniques so that it
is easier for backend writers to override the default behavior.

The default behavior of the hooks preserves the default values of
the related command line options.

NFC
The file was modifiedllvm/include/llvm/CodeGen/TargetRegisterInfo.h (diff)
The file was modifiedllvm/lib/CodeGen/RegAllocGreedy.cpp (diff)
Commit f2f0474c93ee67421fae007528ae4be20ae384f8 by aeubanks
[test] Fix FullUnroll.ll

I believe the intention of this test added in
https://reviews.llvm.org/D71687 was to test LoopFullUnrollPass with
clang's -fno-unroll-loops, not its interaction with optnone. Loop
unrolling passes don't run under optnone/-O0.

Also added back unintentionally removed -disable-loop-unrolling from
https://reviews.llvm.org/D85578.

Reviewed By: echristo

Differential Revision: https://reviews.llvm.org/D86485
The file was modifiedllvm/test/Transforms/LoopUnroll/FullUnroll.ll (diff)
Commit b04c181ed776c344e6f5e2653a22bc6e5746834a by listmail
[AArch64] Enable implicit null check transformation

This change enables the generic implicit null transformation for the AArch64 target. As background for those unfamiliar with our implicit null check support:

    An implicit null check is the use of a signal handler to catch and redirect to a handler a null pointer. Specifically, it's replacing an explicit conditional branch with such a redirect. This is only done for very cold branches under frontend control w/appropriate metadata.
    FAULTING_OP is used to wrap the faulting instruction. It is modelled as being a conditional branch to reflect the fact it can transfer control in the CFG.
    FAULTING_OP does not need to be an analyzable branch to achieve it's purpose. (Or at least, that's the x86 model. I find this slightly questionable.)
    When lowering to MC, we convert the FAULTING_OP back into the actual instruction, record the labels, and lower the original instruction.

As can be seen in the test changes, currently the AArch64 backend does not eliminate the unconditional branch to the fallthrough block. I've tried two approaches, neither of which worked. I plan to return to this in a separate change set once I've wrapped my head around the interactions a bit better. (X86 handles this via AllowModify on analyzeBranch, but adding the obvious code causing BranchFolding to crash. I haven't yet figured out if it's a latent bug in BranchFolding, or something I'm doing wrong.)

Differential Revision: https://reviews.llvm.org/D87851
The file was modifiedllvm/lib/CodeGen/ImplicitNullChecks.cpp (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64AsmPrinter.cpp (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.h (diff)
The file was modifiedllvm/lib/CodeGen/BranchRelaxation.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/implicit-null-check.ll (diff)
Commit 1c466477ad468d8a18c43b738df7b7fc6213e9a8 by zhaoshiz
[RISCV] Support Shadow Call Stack

Currenlty assume x18 is used as pointer to shadow call stack. User shall pass
flags:

"-fsanitize=shadow-call-stack -ffixed-x18"

Runtime supported is needed to setup x18.

If SCS is desired, all parts of the program should be built with -ffixed-x18 to
maintain inter-operatability.

There's no particuluar reason that we must use x18 as SCS pointer. Any register
may be used, as long as it does not have designated purpose already, like RA or
passing call arguments.

Differential Revision: https://reviews.llvm.org/D84414
The file was modifiedclang/lib/Driver/SanitizerArgs.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h (diff)
The file was modifiedclang/test/CodeGen/shadowcallstack-attr.c (diff)
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp (diff)
The file was addedllvm/test/CodeGen/RISCV/shadowcallstack.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp (diff)
The file was modifiedclang/lib/Driver/ToolChain.cpp (diff)
The file was modifiedclang/test/Driver/sanitizer-ld.c (diff)
Commit 8069844577d47f503cb71644f2e58e0237d5b539 by jurahul
[MLIR][TableGen] Automatic detection and elimination of redundant methods

- Change OpClass new method addition to find and eliminate any existing methods that
  are made redundant by the newly added method, as well as detect if the newly added
  method will be redundant and return nullptr in that case.
- To facilitate that, add the notion of resolved and unresolved parameters, where resolved
  parameters have each parameter type known, so that redundancy checks on methods
  with same name but different parameter types can be done.
- Eliminate existing code to avoid adding conflicting/redundant build methods and rely
  on this new mechanism to eliminate conflicting build methods.

Fixes https://bugs.llvm.org/show_bug.cgi?id=47095

Differential Revision: https://reviews.llvm.org/D87059
The file was modifiedmlir/lib/TableGen/OpClass.cpp (diff)
The file was modifiedmlir/include/mlir/TableGen/OpClass.h (diff)
The file was modifiedmlir/test/mlir-tblgen/op-result.td (diff)
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp (diff)
The file was modifiedmlir/test/mlir-tblgen/op-attribute.td (diff)
The file was modifiedmlir/tools/mlir-tblgen/OpFormatGen.cpp (diff)
Commit b4013f9c7febe70bddca16fb80a2e99623528871 by listmail
[MemorySSA] Fix an unused variable warning [NFC]
The file was modifiedllvm/include/llvm/Analysis/MemorySSA.h (diff)
Commit 2c3bc918db35913437e9302b77b11c08eb3ea6e4 by amy.kwan1
[PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang

This patch implements the vec_cntm function prototypes in altivec.h in order to
utilize the vector count mask bits instructions introduced in Power10.

Differential Revision: https://reviews.llvm.org/D82726
The file was modifiedllvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll (diff)
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td (diff)
The file was modifiedclang/test/CodeGen/builtins-ppc-p10vector.c (diff)
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td (diff)
The file was modifiedclang/lib/Headers/altivec.h (diff)
Commit 6f3c0991bf9be48bd18a324c90e4cfcd37f82b96 by amy.kwan1
[PowerPC] Add Set Boolean Condition Instruction Definitions and MC Tests

This patch adds the instruction definitions and assembly/disassembly tests for
the set boolean condition instructions. This also includes the negative, and
reverse variants of the instruction.

Differential Revision: https://reviews.llvm.org/D86252
The file was modifiedllvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt (diff)
The file was modifiedllvm/test/MC/PowerPC/ppc64-encoding-ISA31.s (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td (diff)
Commit 196e2f97b714bb535a39a2daa949e523c21c0269 by Amara Emerson
[AArch64][GlobalISel] clang-format AArch64LegalizerInfo.cpp. NFC.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp (diff)
Commit f5898f8c2def7a1897559a7454086243b7e9ebb6 by Amara Emerson
[AArch64][GlobalISel] Make G_STORE <8 x s8> legal.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir (diff)
Commit 4926a5ee63017396e1c55b1505f9fd2bed858218 by Vedant Kumar
[lldb] Clarify docstring for SBBlock::IsInlined, NFC

Previously, there was a little ambiguity about whether IsInlined should
return true for an inlined lexical block, since technically the lexical
block would not represent an inlined function (it'd just be contained
within one).

Edit suggested by Jim Ingham.
The file was modifiedlldb/bindings/interface/SBBlock.i (diff)
Commit bae63742057785e03732f58d6ed1ec7bda090cc1 by silvasean
[mlir][shape] Add `shape.cstr_require %bool`

This op is a catch-all for creating witnesses from various random kinds
of constraints. In particular, I when dealing with extents directly,
which are of `index` type, one can directly use std ops for calculating
the predicates, and then use cstr_require for the final conversion to a
witness.

Differential Revision: https://reviews.llvm.org/D87871
The file was modifiedmlir/lib/Dialect/Shape/IR/Shape.cpp (diff)
The file was modifiedmlir/include/mlir/Dialect/Shape/IR/ShapeOps.td (diff)
The file was modifiedmlir/test/Dialect/Shape/canonicalize.mlir (diff)
The file was modifiedmlir/test/Dialect/Shape/ops.mlir (diff)
Commit ea237e2c8e5d082715effb9cb64158d7c6894e27 by jurahul
[MLIR] Fix build failure due to https://reviews.llvm.org/D87059.

- Remove spurious ;
- Make comparison object invokable as const.

Differential Revision: https://reviews.llvm.org/D87872
The file was modifiedmlir/include/mlir/TableGen/OpClass.h (diff)
Commit 27f34540ea56207f527dba6bbb9cd25a57be3f62 by mcgrathr
[scudo/standalone] Don't define test main function for Fuchsia

Fuchsia's unit test library provides the main function by default.

Reviewed By: cryptoad

Differential Revision: https://reviews.llvm.org/D87809
The file was modifiedcompiler-rt/lib/scudo/standalone/tests/scudo_unit_test_main.cpp (diff)
Commit 03358becbf22a221d6d965ec8f3f7068668f7d29 by Vitaly Buka
[NFC][Lsan] Fix zero-sized array compilation error
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp (diff)
The file was modifiedclang/lib/Tooling/Syntax/Synthesis.cpp (diff)
Commit 55edf7039e22312790ac950305746262d2856d97 by Vitaly Buka
[NFC] clang-format one line
The file was modifiedclang/lib/Tooling/Syntax/Synthesis.cpp (diff)
Commit 2ffaa9a1732c6f2af514603d25f0e8c238b3dd06 by tejohnson
[sanitizer] Add facility to print the full StackDepot

Split out of D87120 (memory profiler). Added unit testing of the new
printing facility.

Differential Revision: https://reviews.llvm.org/D87792
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stackdepot.h (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_stackdepot_test.cpp (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stackdepotbase.h (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stackdepot.cpp (diff)
Commit f55963d501e46c9453d08a0c764ec40141230966 by lntue
[libc] Add implementation for hypotf

Truncating the sum of squares, and then use shift-and-add algorithm to compute its square root.
Required MPFR testing infra is updated in https://reviews.llvm.org/D87514

Differential Revision: https://reviews.llvm.org/D87516
The file was modifiedlibc/spec/stdc.td (diff)
The file was modifiedlibc/config/linux/api.td (diff)
The file was modifiedlibc/config/linux/x86_64/entrypoints.txt (diff)
The file was modifiedlibc/config/linux/aarch64/entrypoints.txt (diff)
The file was addedlibc/test/src/math/hypotf_test.cpp
The file was modifiedlibc/src/math/CMakeLists.txt (diff)
The file was modifiedlibc/test/src/math/CMakeLists.txt (diff)
The file was addedlibc/src/math/hypotf.h
The file was addedlibc/src/math/hypotf.cpp
Commit 6e475e1288e3e924643a10a426707d704783fcd5 by tejohnson
Revert "[sanitizer] Add facility to print the full StackDepot"

This reverts commit 2ffaa9a1732c6f2af514603d25f0e8c238b3dd06.

There were 2 reported bot failures that need more investigation:

http://lab.llvm.org:8011/builders/sanitizer-windows/builds/69871/steps/stage%201%20check/logs/stdio

   This one is in my new test.

http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fuzzer/builds/39187/steps/check-fuzzer/logs/stdio

   This one seems completely unrelated.
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stackdepot.h (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_stackdepot_test.cpp (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stackdepot.cpp (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stackdepotbase.h (diff)
Commit 992698cfbc898c556fa98962540bd273b115e35c by weiwei64
[AArch64] Emit zext move when the source of the zext is AssertZext or AssertSext

When the source of the zext is AssertZext or AssertSext, it is hard to know any information about the upper 32 bits,
so we should insert a zext move before emitting SUBREG_TO_REG to define the lower 32 bits.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D87771
The file was modifiedllvm/test/CodeGen/AArch64/shift_minsize.ll (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h (diff)

Summary

  1. Add ARM64 Windows on Arm buildbots (details)
Commit 2800bc5c7c1f9efc5e8733ef4d56963758ef24d7 by maxim.kuvyrkov
Add ARM64 Windows on Arm buildbots

This patch adds 2 new machines:
* linaro-armv8-windows-msvc-01
* linaro-armv8-windows-msvc-02
and 2 new builders:
* clang-arm64-windows-msvc
* clang-arm64-windows-msvc-2stage
to test LLVM on Windows on Arm platform.

The machines are Microsoft Surface X Pro laptops configured for 24x7 workload.

The host build environment is bootstrapped based on LLVM 11 custom build and
uses headers and libraries from MS Visual Studio 2019.  To accommodate the custom
setup we add "manual" value for "vs" parameter to ClangBuilder factory, which allows
to use manually pre-configured MSVC environment instead of initializing it during
build by running old-school vcvarsall.bat.

Finally, the bots have known failures in MCJIT unit-tests, which we are working on.
Once the failures are fixed, we'll enable unit-testsuite in both builders.

Reviewed By: gkistanova, omjavaid

Differential Revision: https://reviews.llvm.org/D87186
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)
The file was modifiedzorg/buildbot/builders/ClangBuilder.py (diff)
The file was modifiedbuildbot/osuosl/master/config/slaves.py (diff)