SuccessChanges

Summary

  1. [AArch64] Cortex-A55 scheduler model (details)
  2. [NFC][ARM] More tail predication tests. (details)
  3. [llvm-readelf/obj] - Stop printing invalid names for unnamed section symbols. (details)
  4. Do not dereference an array out of bound just to take its address (details)
  5. [ARM] Select f32 constants with vmov.f16 (details)
  6. [mlir][VectorOps] Loosen restrictions on vector.reduction types (details)
  7. Recommit "[SCEV] Look through single value PHIs." (details)
  8. [AST] Reduce the size of TemplateArgumentLocInfo. (details)
  9. Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit" (details)
  10. Fix buildbot. (details)
  11. [MLIR] Fix typo and expand gpu.host_register description. (details)
  12. [SyntaxTree][NFC] follow naming convention + remove auto on empty vector declaration (details)
  13. [SVE] Use NEON for extract_vector_elt when the index is in range. (details)
  14. [SVE] Change definition of reduction ISD nodes to have an SVE vector result type. (details)
  15. [clang-tidy] New check cppcoreguidelines-prefer-member-initializer (details)
  16. [Statepoints][ISEL] gc.relocate uniquification should be based on SDValue, not IR Value. (details)
  17. [gn build] Port 4fc0214a101 (details)
  18. DWARFYAML::emitDebugSections - remove unnecessary cantFail(success) call. NFCI. (details)
  19. [llvm-readobj/libObject] - Get rid of `FirstSym` argument. NFCI. (details)
  20. Change comments about order of classes in superclass list. (details)
  21. DWARFEmitter.cpp - use auto const& iterators in for-range loops to avoid copies. NFCI. (details)
  22. [ASTImporter] Refactor IsStructurallyEquivalent's Decl overloads to be more consistent (details)
  23. [AIX][Clang][Driver] Add handling of nostartfiles option (details)
  24. [SLP] Allow reordering of vectorization trees with reused instructions. (details)
  25. [analyzer][solver] Fix issue with symbol non-equality tracking (details)
  26. Update update_analyze_test_checks.py to support API changes from D83004 (details)
  27. [CostModel][X86] Add some select shuffle costs tests for D87884 (details)
  28. [mlir][openacc] Add attributes to parallel op async, wait and self clauses (details)
  29. [LoopSimplifyCFG][NewPM] Rename simplify-cfg -> loop-simplifycfg (details)
  30. [PowerPC] Add vector pair load/store instructions and vector pair register class (details)
  31. [LLD][ELF][test] Fix CHECKs in map-file test (details)
  32. [TextAPI] clean up auto usages in tests, NFC (details)
  33. [SVE][CodeGen] Mark ptrue/pfalse instructions as rematerializable (details)
  34. ProfileSummary.cpp - use auto const& iterator in for-range loop to avoid copies. NFCI. (details)
  35. Fix Wdocumentation unknown parameter warnings. NFCI. (details)
  36. MachineCSE.cpp - use auto const& iterator in for-range loop to avoid copies. NFCI. (details)
  37. [clang] Fix a misleading variable name. NFC. (details)
  38. [Sema] Split special builtin type lookups into a separate function (details)
  39. SLPVectorizer.cpp - fix include ordering. NFCI. (details)
  40. TargetPassConfig.cpp - use auto const& iterator in for-range loop to avoid copies. NFCI. (details)
  41. [ARM][CMSE] Issue an error if passing arguments through memory across (details)
Commit 4b8ade837e36b7f0181ce86fc23f33851d0fdd35 by sjoerd.meijer
[AArch64] Cortex-A55 scheduler model

This is an initial commit adding the A55 model, but it isn't used/enabled yet.
We will follow up on this to improve the model, then flip the switch.

The optimisation guide describing Cortex-A55 micro-architecture in more detail
can be found here:

https://static.docs.arm.com/epm128372/20/arm_cortex_a55_software_optimization_guide_v2.pdf

Original patch by Javed Absar.

Differential Revision: https://reviews.llvm.org/D46884
The file was modifiedllvm/lib/Target/AArch64/AArch64.td (diff)
The file was addedllvm/lib/Target/AArch64/AArch64SchedA55.td
Commit 13c73632c7cfcc2c8e70c93781d8fb9872153ede by sam.parker
[NFC][ARM] More tail predication tests.

Add mir tests for use/def of P0.
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir (diff)
Commit 095f6fbbd7b61af205d761f6951a869ec4a61722 by grimar
[llvm-readelf/obj] - Stop printing invalid names for unnamed section symbols.

We have an issue with `ELFDumper<ELFT>::getSymbolSectionName`:
1) It is used deeply for both LLVM/GNU styles and might return LLVM-style only
   values to describe symbols: "Undefined", "Processor Specific", "Absolute", etc.

2) `getSymbolSectionName` is used by `getFullSymbolName` and these special values
   might appear instead of symbol names in many places.
   This occurs for unnamed section symbols currently.

This patch extracts the LLVM specific logic to `LLVMStyle<ELFT>::printSymbolSection`,
which seems to be the only place where we want to print the special values mentioned.
It also adds a meaningful new warning that is reported when we are unable to get
a section index for a section symbol.

Differential revision: https://reviews.llvm.org/D87764
The file was modifiedllvm/test/tools/llvm-readobj/ELF/symbol-shndx.test (diff)
The file was modifiedllvm/test/tools/llvm-readobj/ELF/mips-plt.test (diff)
The file was modifiedllvm/test/tools/llvm-readobj/ELF/dyn-symbols.test (diff)
The file was modifiedllvm/test/tools/llvm-readobj/ELF/hash-symbols.test (diff)
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp (diff)
The file was modifiedllvm/test/tools/llvm-readobj/ELF/mips-got.test (diff)
Commit 2a774411174466010c69a2460c81b8d0d4f7165f by sguelton
Do not dereference an array out of bound just to take its address

This is UB by the standard, and caught by the libstdc++ asserts

Differential Revision: https://reviews.llvm.org/D87892
The file was modifiedflang/lib/Parser/token-sequence.cpp (diff)
Commit f4c5cadbcbb41f13cff0905449cfff4aef6a083c by david.green
[ARM] Select f32 constants with vmov.f16

This adds lowering for f32 values using the vmov.f16, which zeroes the
top bits whilst setting the lower bits to a pattern. This range of
values does not often come up, except where a f16 constant value has
been converted to a f32.

Differential Revision: https://reviews.llvm.org/D87790
The file was modifiedllvm/test/CodeGen/ARM/fp16-bitcast.ll (diff)
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp (diff)
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h (diff)
The file was modifiedllvm/test/CodeGen/ARM/cmse-clear-float-hard.ll (diff)
The file was modifiedllvm/lib/Target/ARM/ARMInstrVFP.td (diff)
Commit 2d76274b99f2c09cdd94863d6e2e48a06f863f2a by benny.kra
[mlir][VectorOps] Loosen restrictions on vector.reduction types

LLVM can deal with any integer or float type, don't arbitrarily restrict
it to f32/f64/i32/i64.

Differential Revision: https://reviews.llvm.org/D88010
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp (diff)
The file was modifiedmlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir (diff)
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp (diff)
Commit 11dccf8d3aa5d55210f8b886fb21926c7a8353ca by flo
Recommit "[SCEV] Look through single value PHIs."

This commit was originally because it was suspected to cause a crash,
but a reproducer did not surface.

A crash that was exposed by this change was fixed in 1d8f2e52925b.

This reverts the revert commit 0581c0b0eeba03da590d1176a4580cf9b9e8d1e3.
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp (diff)
The file was modifiedllvm/test/Analysis/ScalarEvolution/solve-quadratic-i1.ll (diff)
The file was modifiedllvm/test/Transforms/LoopStrengthReduce/funclet.ll (diff)
The file was modifiedllvm/test/Analysis/ScalarEvolution/solve-quadratic-overflow.ll (diff)
Commit af29591650c43bd3bdc380c9d47b8bfd0f1664a2 by hokein.wu
[AST] Reduce the size of TemplateArgumentLocInfo.

allocate the underlying data of Template kind separately, this would reduce AST
memory usage

- TemplateArgumentLocInfo 24 => 8 bytes
- TemplateArgumentLoc  48 => 32 bytes
- DynTypeNode 56 => 40 bytes

ASTContext::.getASTAllocatedMemory changes:
  SemaDecl.cpp 255.5 MB => 247.5MB
  SemaExpr.cpp 293.5 MB => 283.5MB

Differential Revision: https://reviews.llvm.org/D87080
The file was modifiedclang/include/clang/AST/Expr.h (diff)
The file was modifiedclang/include/clang/AST/TemplateBase.h (diff)
The file was modifiedclang/lib/AST/TemplateBase.cpp (diff)
The file was modifiedclang/lib/Sema/SemaTemplateDeduction.cpp (diff)
The file was modifiedclang/lib/Sema/TreeTransform.h (diff)
The file was modifiedclang/lib/Sema/SemaTemplate.cpp (diff)
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp (diff)
The file was modifiedclang/lib/AST/TypeLoc.cpp (diff)
The file was modifiedclang/lib/Sema/SemaTemplateVariadic.cpp (diff)
The file was modifiedclang/lib/Serialization/ASTReader.cpp (diff)
The file was modifiedclang/lib/AST/ASTImporter.cpp (diff)
Commit 17dc729bd42947b839c9717a2efa9e1e04248616 by pifon
Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit"

This reverts commit 0345d88de654259ae90494bf9b015416e2cccacb.

Google internal backend uses EntrySU, we are looking into removing
dependency on it.

Differential Revision: https://reviews.llvm.org/D88018
The file was modifiedllvm/lib/CodeGen/PostRASchedulerList.cpp (diff)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineScheduler.h (diff)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp (diff)
The file was modifiedllvm/include/llvm/CodeGen/MachineScheduler.h (diff)
The file was modifiedllvm/lib/CodeGen/MachineScheduler.cpp (diff)
The file was modifiedllvm/lib/CodeGen/ScheduleDAG.cpp (diff)
The file was modifiedllvm/lib/CodeGen/MacroFusion.cpp (diff)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (diff)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (diff)
The file was modifiedllvm/include/llvm/CodeGen/ScheduleDAG.h (diff)
The file was modifiedllvm/lib/CodeGen/ScheduleDAGInstrs.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp (diff)
Commit 41a8bbad5e52a94a485c5bfe3d7871784fe6d8ed by hokein.wu
Fix buildbot.

TemplateArgumentLocInfo cannot result in a constant expression anymore
after D87080.
The file was modifiedclang/include/clang/AST/TemplateBase.h (diff)
Commit 9ba3b7449d30c7a7b9be77ef3ac4016ba263b619 by csigg
[MLIR] Fix typo and expand gpu.host_register description.

See comments in https://reviews.llvm.org/D85631.

Reviewed By: herhut

Differential Revision: https://reviews.llvm.org/D86214
The file was modifiedmlir/include/mlir/Dialect/GPU/GPUOps.td (diff)
The file was modifiedmlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp (diff)
Commit 87f0b51d68de40e7106be89d934b5191d983e3d5 by ecaldas
[SyntaxTree][NFC] follow naming convention + remove auto on empty vector declaration

Differential Revision: https://reviews.llvm.org/D88004
The file was modifiedclang/lib/Tooling/Syntax/Tree.cpp (diff)
The file was modifiedclang/lib/Tooling/Syntax/BuildTree.cpp (diff)
The file was modifiedclang/lib/Tooling/Syntax/Nodes.cpp (diff)
Commit 6457455248d5b83a7e4274f06b6313b15cd51421 by paul.walker
[SVE] Use NEON for extract_vector_elt when the index is in range.

Patch also adds missing patterns for unpacked vector types and
extracts of element zero.

Differential Revision: https://reviews.llvm.org/D87842
The file was modifiedllvm/test/CodeGen/AArch64/sve-insert-element.ll (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td (diff)
The file was modifiedllvm/test/CodeGen/AArch64/sve-split-extract-elt.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/sve-extract-element.ll (diff)
Commit f3fa954b5b19acdd4b95ff2ca1ff4f74f4b6b21b by paul.walker
[SVE] Change definition of reduction ISD nodes to have an SVE vector result type.

The current nodes, AArch64::SMAXV_PRED for example, are defined to
return a NEON vector result.  This is incorrect because they modify
the complete SVE register and are thus changed to represent such.

This patch also adds nodes for UADDV_PRED and SADDV_PRED, which
unifies the handling of all SVE reductions.

NOTE: Floating-point reductions are already implemented correctly,
so this patch is essentially making everything consistent with those.

Differential Revision: https://reviews.llvm.org/D87843
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td (diff)
The file was modifiedllvm/test/CodeGen/AArch64/sve-int-reduce-pred.ll (diff)
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h (diff)
Commit 4fc0214a10140fa77449677e8094ea22d3d17701 by adam.balogh
[clang-tidy] New check cppcoreguidelines-prefer-member-initializer

Finds member initializations in the constructor body which can be placed
into the initialization list instead. This does not only improves the
readability of the code but also affects positively its performance.
Class-member assignments inside a control statement or following the
first control statement are ignored.

Differential Revision: https://reviews.llvm.org/D71199
The file was modifiedclang-tools-extra/clang-tidy/cppcoreguidelines/CppCoreGuidelinesTidyModule.cpp (diff)
The file was addedclang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines-prefer-member-initializer.rst
The file was modifiedclang-tools-extra/docs/ReleaseNotes.rst (diff)
The file was addedclang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.h
The file was addedclang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-prefer-member-initializer-modernize-use-default-member-init.cpp
The file was modifiedclang-tools-extra/clang-tidy/cppcoreguidelines/CMakeLists.txt (diff)
The file was addedclang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.cpp
The file was addedclang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-prefer-member-initializer.cpp
The file was addedclang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-prefer-member-initializer-modernize-use-default-member-init-assignment.cpp
Commit ee86688b81751c57ca5b24e462194ea5522345c4 by dantrushin
[Statepoints][ISEL] gc.relocate uniquification should be based on SDValue, not IR Value.

When exporting statepoint results to virtual registers we try to avoid
generating exports for duplicated inputs. But we erroneously use
IR Value* to check if inputs are duplicated. Instead, we should use
SDValue, because even different IR values can get lowered to the same
SDValue.
I'm adding a (degenerate) test case which emphasizes importance of this
feature for invoke statepoints.
If we fail to export only unique values we will end up with something
like that:

  %0 = STATEPOINT
  %1 = COPY %0

landing_pad:
  <use of %1>

And when exceptional path is taken, %1 is left uninitialized (COPY is never
execute).

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D87695
The file was modifiedllvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/X86/statepoint-vreg-details.ll (diff)
Commit 6d2bf5e3c89b08c64404045640e4a5a2189acbe4 by llvmgnsyncbot
[gn build] Port 4fc0214a101
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clang-tidy/cppcoreguidelines/BUILD.gn (diff)
Commit 82042a2c9b2330cfb4621322474448567c52f7b6 by llvm-dev
DWARFYAML::emitDebugSections - remove unnecessary cantFail(success) call. NFCI.

As mentioned on rG6bb912336804.
The file was modifiedllvm/lib/ObjectYAML/DWARFEmitter.cpp (diff)
Commit df3e903655e2499968fc7af64fb5fa52b2ee79bb by grimar
[llvm-readobj/libObject] - Get rid of `FirstSym` argument. NFCI.

We use `FirstSym` argument in `getExtendedSymbolTableIndex` to calculate
a symbol index:

```
&Sym - &FirstSym
```

Instead, we could pass the symbol index directly.
This is what this patch does, it allows to simplify another llvm-readobj API.

Differential revision: https://reviews.llvm.org/D88016
The file was modifiedllvm/include/llvm/Object/ELF.h (diff)
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp (diff)
Commit bd55d5b2a11030dc7a93008275c533bbdb748c72 by paul
Change comments about order of classes in superclass list.
The file was modifiedllvm/include/llvm/TableGen/Record.h (diff)
The file was modifiedllvm/lib/TableGen/Record.cpp (diff)
Commit 2ef2abdec20e7275ae719fa8be920482f08da1f0 by llvm-dev
DWARFEmitter.cpp - use auto const& iterators in for-range loops to avoid copies. NFCI.
The file was modifiedllvm/lib/ObjectYAML/DWARFEmitter.cpp (diff)
Commit 7c4575e15f065312ad40ebe0d1ec1e1ffa4c6628 by Raphael Isemann
[ASTImporter] Refactor IsStructurallyEquivalent's Decl overloads to be more consistent

There are several `::IsStructurallyEquivalent` overloads for Decl subclasses
that are used for comparing declarations. There is also one overload that takes
just two Decl pointers which ends up queuing the passed Decls to be later
compared in `CheckKindSpecificEquivalence`.

`CheckKindSpecificEquivalence` implements the dispatch logic for the different
Decl subclasses. It is supposed to hand over the queued Decls to the
subclass-specific `::IsStructurallyEquivalent` overload that will actually
compare the Decl instance. It also seems to implement a few pieces of actual
node comparison logic inbetween the dispatch code.

This implementation causes that the different overloads of
`::IsStructurallyEquivalent` do different (and sometimes no) comparisons
depending on which overload of `::IsStructurallyEquivalent` ends up being
called.

For example, if I want to compare two FieldDecl instances, then I could either
call the `::IsStructurallyEquivalent` with `Decl *` or with `FieldDecl *`
parameters. The overload that takes FieldDecls is doing a correct comparison.
However, the `Decl *` overload just queues the Decl pair.
`CheckKindSpecificEquivalence` has no dispatch logic for `FieldDecl`, so it
always returns true and never does any actual comparison.

On the other hand, if I try to compare two FunctionDecl instances the two
possible overloads of `::IsStructurallyEquivalent` have the opposite behaviour:
The overload that takes `FunctionDecl` pointers isn't comparing the names of the
FunctionDecls while the overload taking a plain `Decl` ends up comparing the
function names (as the comparison logic for that is implemented in
`CheckKindSpecificEquivalence`).

This patch tries to make this set of functions more consistent by making
`CheckKindSpecificEquivalence` a pure dispatch function without any
subclass-specific comparison logic. Also the dispatch logic is now autogenerated
so it can no longer miss certain subclasses.

The comparison code from `CheckKindSpecificEquivalence` is moved to the
respective `::IsStructurallyEquivalent` overload so that the comparison result
no longer depends if one calls the `Decl *` overload or the overload for the
specific subclass. The only difference is now that the `Decl *` overload is
queuing the parameter while the subclass-specific overload is directly doing the
comparison.

`::IsStructurallyEquivalent` is an implementation detail and I don't think the
behaviour causes any bugs in the current implementation (as carefully calling
the right overload for the different classes works around the issue), so the
test for this change is that I added some new code for comparing `MemberExpr`.
The new comparison code always calls the dispatching overload and it previously
failed as the dispatch didn't support FieldDecls.

Reviewed By: martong, a_sidorin

Differential Revision: https://reviews.llvm.org/D87619
The file was modifiedclang/unittests/AST/StructuralEquivalenceTest.cpp (diff)
The file was modifiedclang/lib/AST/ASTStructuralEquivalence.cpp (diff)
Commit 699089f2a9702baa987dc2dbe915a2c845c7027f by daltenty
[AIX][Clang][Driver] Add handling of nostartfiles option

Reviewed By: jasonliu

Differential Revision: https://reviews.llvm.org/D87904
The file was modifiedclang/test/Driver/aix-ld.c (diff)
The file was modifiedclang/lib/Driver/ToolChains/AIX.cpp (diff)
Commit 3ff07fcd542ebef657bb93fe8ee1750527210b94 by a.bataev
[SLP] Allow reordering of vectorization trees with reused instructions.

If some leaves have the same instructions to be vectorized, we may
incorrectly evaluate the best order for the root node (it is built for the
vector of instructions without repeated instructions and, thus, has less
elements than the root node). In this case we just can not try to reorder
the tree + we may calculate the wrong number of nodes that requre the
same reordering.
For example, if the root node is \<a+b, a+c, a+d, f+e\>, then the leaves
are \<a, a, a, f\> and \<b, c, d, e\>. When we try to vectorize the first
leaf, it will be shrink to \<a, b\>. If instructions in this leaf should
be reordered, the best order will be \<1, 0\>. We need to extend this
order for the root node. For the root node this order should look like
\<3, 0, 1, 2\>. This patch allows extension of the orders of the nodes
with the reused instructions.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D45263
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll (diff)
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/jumbled_store_crash.ll (diff)
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp (diff)
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll (diff)
Commit 0c4f91f84b2efe8975848a7a13c08d7479abe752 by gabor.marton
[analyzer][solver] Fix issue with symbol non-equality tracking

We should track non-equivalency (disequality) in case of greater-then or
less-then assumptions.

Differential Revision: https://reviews.llvm.org/D88019
The file was modifiedclang/test/Analysis/equality_tracking.c (diff)
The file was modifiedclang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp (diff)
Commit 2174efb10480ac374364eb9eef1a5ae79c7b16e2 by llvm-dev
Update update_analyze_test_checks.py to support API changes from D83004
The file was modifiedllvm/utils/update_analyze_test_checks.py (diff)
Commit 18a3ebcd3016d9bd1112d6804654758afabf8a98 by llvm-dev
[CostModel][X86] Add some select shuffle costs tests for D87884
The file was addedllvm/test/Analysis/CostModel/X86/shuffle-select.ll
Commit 2e2bcee05876305cb9b21b6b5e8e48dc6da58ede by clementval
[mlir][openacc] Add attributes to parallel op async, wait and self clauses

Add attributes for the async, wait and self clauses. These clauses can be present without
values. When this is the case they are modelled with an attribute instead of operands.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D87991
The file was modifiedmlir/test/Dialect/OpenACC/ops.mlir (diff)
The file was modifiedmlir/include/mlir/Dialect/OpenACC/OpenACCOps.td (diff)
Commit 5249e6f24876ea577de51ad2f9166a2e466171b9 by aeubanks
[LoopSimplifyCFG][NewPM] Rename simplify-cfg -> loop-simplifycfg

This matches the legacy PM name and makes all tests in
Transforms/LoopSimplifyCFG pass under NPM.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D87948
The file was modifiedllvm/test/Transforms/LICM/hoist-bitcast-load.ll (diff)
The file was modifiedllvm/test/Transforms/LoopSimplifyCFG/live_block_marking.ll (diff)
The file was modifiedllvm/test/Transforms/LoopSimplifyCFG/merge-header.ll (diff)
The file was modifiedllvm/lib/Passes/PassRegistry.def (diff)
The file was modifiedllvm/test/Transforms/LoopSimplifyCFG/constant-fold-branch.ll (diff)
The file was modifiedllvm/test/Transforms/LoopSimplifyCFG/irreducible_cfg.ll (diff)
The file was modifiedllvm/test/Transforms/LoopSimplifyCFG/handle_dead_exits.ll (diff)
The file was modifiedllvm/test/Transforms/LoopSimplifyCFG/update_parents.ll (diff)
The file was modifiedllvm/test/Transforms/GVN/preserve-analysis.ll (diff)
The file was modifiedllvm/test/Transforms/LICM/hoist-deref-load.ll (diff)
The file was modifiedllvm/test/Transforms/LoopSimplifyCFG/lcssa.ll (diff)
The file was modifiedllvm/test/Transforms/LoopSimplifyCFG/mssa_update.ll (diff)
The file was modifiedllvm/test/Transforms/LoopSimplifyCFG/phi_with_duplicating_inputs.ll (diff)
The file was modifiedllvm/test/Transforms/SimpleLoopUnswitch/trivial-unswitch-iteration.ll (diff)
Commit 1372e23c7d4b25fd23689842246e66f70c949b46 by baptiste.saleil
[PowerPC] Add vector pair load/store instructions and vector pair register class

This patch adds support for the lxvp, lxvpx, plxvp, stxvp, stxvpx and pstxvp
instructions in the PowerPC backend. These instructions allow loading and
storing VSX register pairs. This patch also adds the VSRp register class
definition needed for these instructions.

Differential Revision: https://reviews.llvm.org/D84359
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.h (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td (diff)
The file was modifiedllvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (diff)
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h (diff)
The file was modifiedllvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.td (diff)
The file was modifiedllvm/test/MC/PowerPC/ppc64-encoding-ISA31.s (diff)
The file was modifiedllvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt (diff)
The file was modifiedllvm/utils/TableGen/CodeGenTarget.cpp (diff)
Commit 0a6860521eb8b8d5d2d205f50ea527033056af24 by grimar
[LLD][ELF][test] Fix CHECKs in map-file test

A repeated typo in lld/test/ELF/map-file.s prevented a number of checks from being executed.

CHECk-NEXT -> CHECK-NEXT
    ^             ^

After correcting the typo, a small adjustment was needed to match the size of the synthetic .comment section (which always contains "LLD 1.0" in the test environment).

Differential revision: https://reviews.llvm.org/D88023
The file was modifiedlld/test/ELF/map-file.s (diff)
Commit 0b15cb70d318255814c0614a978b6920ba075fa2 by Cyndy Ishida
[TextAPI] clean up auto usages in tests, NFC
The file was modifiedllvm/unittests/TextAPI/TextStubHelpers.h (diff)
The file was modifiedllvm/unittests/TextAPI/TextStubV3Tests.cpp (diff)
The file was modifiedllvm/unittests/TextAPI/TextStubV4Tests.cpp (diff)
Commit 96e52c13640ba60417ebd1d03cee79a2c0089308 by david.sherwood
[SVE][CodeGen] Mark ptrue/pfalse instructions as rematerializable
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td (diff)
Commit 53f1748c131c8d7ff0bb5e5c77132780c5d1fbc7 by llvm-dev
ProfileSummary.cpp - use auto const& iterator in for-range loop to avoid copies. NFCI.
The file was modifiedllvm/lib/IR/ProfileSummary.cpp (diff)
Commit 604206b61cb948c01b438dd06b3b7bc837e99455 by llvm-dev
Fix Wdocumentation unknown parameter warnings. NFCI.
The file was modifiedllvm/include/llvm/Analysis/IRSimilarityIdentifier.h (diff)
Commit ce294ff8cddf110cefd5955cf30c575c7838b452 by llvm-dev
MachineCSE.cpp - use auto const& iterator in for-range loop to avoid copies. NFCI.
The file was modifiedllvm/lib/CodeGen/MachineCSE.cpp (diff)
Commit 474d527c28f4e88ffda7b82e93e351aec2602380 by ikudrin
[clang] Fix a misleading variable name. NFC.

The variable is true when frame pointers should be omitted in leaf
functions, not kept.

Differential Revision: https://reviews.llvm.org/D88021
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp (diff)
Commit f91f28c350df6815d37c521e8f3dc0641a3ca467 by raul
[Sema] Split special builtin type lookups into a separate function

In case further such cases appear in the future we've got a generic function to add them to.
Additionally changed the ObjC special case to check the language and the identifier builtin ID instead of the name.

Addresses the cleanup suggestion from D87917.

Reviewed By: rjmccall

Differential Revision: https://reviews.llvm.org/D87983
The file was modifiedclang/lib/Sema/SemaLookup.cpp (diff)
The file was modifiedclang/include/clang/Sema/Sema.h (diff)
The file was modifiedclang/lib/Sema/SemaDecl.cpp (diff)
Commit 3ddecfd220079cd37d2d08810c3940ffcde57953 by llvm-dev
SLPVectorizer.cpp - fix include ordering. NFCI.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp (diff)
Commit 3ae07b2a33f5541b36913280564420aaa46a54f8 by llvm-dev
TargetPassConfig.cpp - use auto const& iterator in for-range loop to avoid copies. NFCI.
The file was modifiedllvm/lib/CodeGen/TargetPassConfig.cpp (diff)
Commit 742250bf62a92647d3462d1e0b75940bc0914fcb by momchil.velikov
[ARM][CMSE] Issue an error if passing arguments through memory across
security boundary

It was never supported and that part was accidentally omitted when
upstreaming D76518.

Differential Revision: https://reviews.llvm.org/D86478

Change-Id: If6ba9506eb0431c87a1d42a38aa60e47ce263039
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp (diff)
The file was addedllvm/test/CodeGen/ARM/cmse-errors.ll

Summary

  1. LNT CTMark: Update default SUBMIT_NAME and add SUBMIT_ORDER (details)
  2. jenkins/jobs: Move the lnt-ctmark-* jobs to green-dragon-12 (details)
Commit 1e8d9e10ded4e03db4e13a26b74e1247f4b5312a by Azharuddin Mohammed
LNT CTMark: Update default SUBMIT_NAME and add SUBMIT_ORDER

- Include the node name in the SUBMIT_NAME
- Add SUBMIT_ORDER (based on GIT_DISTANCE)
The file was modifiedtasks/lnt-ctmark.sh (diff)
Commit 76a1ebd3ccf61650f80f2787d65b5f69cb51485d by Azharuddin Mohammed
jenkins/jobs: Move the lnt-ctmark-* jobs to green-dragon-12
The file was modifiedzorg/jenkins/jobs/jobs/lnt-ctmark-aarch64-O3-flto (diff)
The file was modifiedzorg/jenkins/jobs/jobs/lnt-ctmark-aarch64-O0-g (diff)
The file was modifiedzorg/jenkins/jobs/jobs/lnt-ctmark-aarch64-Os (diff)
The file was modifiedzorg/jenkins/jobs/jobs/lnt-ctmark-aarch64-Oz (diff)