SuccessChanges

Summary

  1. Revert "[RISCV][ASAN] implementation of ThreadSelf  for riscv64" (details)
  2. [NFC] Reformat preprocessor directives (details)
  3. [RISCV][ASAN] implementation of ThreadSelf  for riscv64 (details)
  4. [mlir][Linalg] Add pattern to fold linalg.tensor_reshape that add unit extent dims. (details)
  5. [AMDGPU] Fix merging m0 inits (details)
  6. [SVE] Fix InstCombinerImpl::PromoteCastOfAllocation for scalable vectors (details)
  7. Revert "[libc++] Implement LWG1203" (details)
  8. [SVE] Make EVT::getScalarSizeInBits and others consistent with Type::getScalarSizeInBits (details)
  9. [analyzer][StdLibraryFunctionsChecker] Fix getline/getdelim signatures (details)
  10. [analyzer][StdLibraryFunctionsChecker] Separate the signature from the summaries (details)
  11. [llvm-readelf/obj] - Cleanup the code. NFCI. (details)
  12. [AMDGPU] Insert waitcnt after returning from call (details)
  13. [llvm-readelf/obj] - Print section symbol names properly when dumping relocations. (details)
  14. [llvm-readelf/obj] - Fix extended section symbol indices printed in warnings for MIPS GOT/PLT entries. (details)
  15. [SVE][CodeGen] Lower legal integer -> floating point conversions (details)
  16. [flang] CHARACTER(*) return does not require explicit interface (details)
  17. [CUDA][HIP] Fix static device var used by host code only (details)
  18. [OpenMP][flang]Lower NUM_THREADS clause for parallel construct (details)
  19. [mlir] Added support for f64 memref printing in runner utils (details)
  20. [flang] Removed OpenMP lowering unittests (details)
  21. [NFCI][flang] Renamed a variable name to a more descriptive name (details)
  22. [libc++] Re-apply fdc41e11f (LWG1203) without breaking the C++11 build (details)
  23. [lldb] Fix GetRemoteSharedModule fallback logic (details)
  24. AMDGPU: Check global FP atomics match default FP mode (details)
  25. GlobalISel: Fix truncating shift amount in trunc (shl) combine (details)
  26. Fix typos in ASTMatchers.h; NFC (details)
Commit 1fbb5969424493344f1159d53bda5a640e3b27ae by Vitaly Buka
Revert "[RISCV][ASAN] implementation of ThreadSelf  for riscv64"

Merged two unrelated commits

This reverts commit 00f6ebef6e347e0d24a8f940fe43656719e88cb8.
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp (diff)
Commit d721a2bc335ad01ff6b3838bc4759cfc35b6c8fa by Vitaly Buka
[NFC] Reformat preprocessor directives
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp (diff)
Commit 809a42e3d53518b824aad28882f9f9397f25b5b3 by Vitaly Buka
[RISCV][ASAN] implementation of ThreadSelf  for riscv64

[6/11] patch series to port ASAN for riscv64

Depends On D87574

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D87575
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp (diff)
Commit b62f9f4407a5ed6e5722e177e906efcebebce9eb by ravishankarm
[mlir][Linalg] Add pattern to fold linalg.tensor_reshape that add unit extent dims.

A sequence of two reshapes such that one of them is just adding unit
extent dims can be folded to a single reshape.

Differential Revision: https://reviews.llvm.org/D88057
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp (diff)
The file was modifiedmlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir (diff)
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp (diff)
Commit 8d7fd73c3a8ce069cfe48dfcf949b4a59c05c673 by Piotr Sobczak
[AMDGPU] Fix merging m0 inits

Fix incorrect merges of m0 inits in loops.

It was assumed that if a clobbering instruction appears in
the same block as an init and the clobbering instruction
does not dominate the init then it does not interfere with
init.

This does not work in the presence of loops, where in this
scenario, the clobbering instruction does interfere with
the init in another iteration.

To fix this, do not check for block equality and defer the
decision to the predecessor check.

Differential Revision: https://reviews.llvm.org/D87882
The file was modifiedllvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/merge-m0.mir (diff)
Commit 59c4d5aad060927fa95b917c11aad4e310849a4b by david.sherwood
[SVE] Fix InstCombinerImpl::PromoteCastOfAllocation for scalable vectors

In this patch I've fixed some warnings that arose from the implicit
cast of TypeSize -> uint64_t. I tried writing a variety of different
cases to show how this optimisation might work for scalable vectors
and found:

1. The optimisation does not work for cases where the cast type
is scalable and the allocated type is not. This because we need to
know how many times the cast type fits into the allocated type.
2. If we pass all the various checks for the case when the allocated
type is scalable and the cast type is not, then when creating the
new alloca we have to take vscale into account. This leads to
sub-optimal IR that is worse than the original IR.
3. For the remaining case when both the alloca and cast types are
scalable it is hard to find examples where the optimisation would
kick in, except for simple bitcasts, because we typically fail the
ABI alignment checks.

For now I've changed the code to bail out if only one of the alloca
and cast types is scalable. This means we continue to support the
existing cases where both types are fixed, and also the specific case
when both types are scalable with the same size and alignment, for
example a simple bitcast of an alloca to another type.

I've added tests that show we don't attempt to promote the alloca,
except for simple bitcasts:

  Transforms/InstCombine/AArch64/sve-cast-of-alloc.ll

Differential revision: https://reviews.llvm.org/D87378
The file was addedllvm/test/Transforms/InstCombine/AArch64/sve-cast-of-alloc.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCasts.cpp (diff)
Commit e46c1def523323eedfad1174fd2fabbece8f40cc by Raphael Isemann
Revert "[libc++] Implement LWG1203"

This reverts commit fdc41e11f9687a50c97e2a59663bf2d541ff5489. It causes the
libcxx/modules/stds_include.sh.cpp test to fail with:
libcxx/include/ostream:1039:45: error: no template named 'enable_if_t'; did you mean 'enable_if'?
template <class _Stream, class _Tp, class = enable_if_t<

Still investigating what's causing this and reverting in the meantime to get
the bots green again.
The file was removedlibcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/rvalue.pass.cpp
The file was modifiedlibcxx/www/cxx2a_status.html (diff)
The file was addedlibcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/CharT_pointer.pass.cpp
The file was removedlibcxx/test/std/input.output/iostream.format/input.streams/istream.rvalue/not_istreamable.verify.cpp
The file was modifiedlibcxx/include/istream (diff)
The file was modifiedlibcxx/include/ostream (diff)
The file was removedlibcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/not_ostreamable.verify.cpp
The file was modifiedlibcxx/test/std/input.output/iostream.format/input.streams/istream.rvalue/rvalue.pass.cpp (diff)
Commit e077367a28102128483f4b2555d2ad31e21b1965 by david.sherwood
[SVE] Make EVT::getScalarSizeInBits and others consistent with Type::getScalarSizeInBits

An existing function Type::getScalarSizeInBits returns a uint64_t
instead of a TypeSize class because the caller is requesting a
scalar size, which cannot be scalable. This patch makes other
similar functions requesting a scalar size consistent with that,
thereby eliminating more than 1000 implicit TypeSize -> uint64_t
casts.

Differential revision: https://reviews.llvm.org/D87889
The file was modifiedllvm/include/llvm/Support/MachineValueType.h (diff)
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp (diff)
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAGNodes.h (diff)
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp (diff)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (diff)
The file was modifiedllvm/include/llvm/CodeGen/ValueTypes.h (diff)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (diff)
Commit d63a945a13048b66f06e222d8b0810d7db9592f6 by gabor.marton
[analyzer][StdLibraryFunctionsChecker] Fix getline/getdelim signatures

It is no longer needed to add summaries of 'getline' for different
possible underlying types of ssize_t. We can just simply lookup the
type.

Differential Revision: https://reviews.llvm.org/D88092
The file was modifiedclang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp (diff)
The file was modifiedclang/test/Analysis/std-c-library-functions.c (diff)
Commit 11d2e63ab0060c656398afd8ea26760031a9fb96 by gabor.marton
[analyzer][StdLibraryFunctionsChecker] Separate the signature from the summaries

The signature should not be part of the summaries as many FIXME comments
suggests. By separating the signature, we open up the way to a generic
matching implementation which could be used later under the hoods of
CallDescriptionMap.

Differential Revision: https://reviews.llvm.org/D88100
The file was modifiedclang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp (diff)
Commit 310af42ed9ab259ad05ed46d459203b3473ba66e by grimar
[llvm-readelf/obj] - Cleanup the code. NFCI.

This:
1) Replaces pointers with references in many places.
2) Adds few TODOs about fixing possible unhandled errors (in ARMEHABIPrinter.h).
3) Replaces `auto`s with actual types.
4) Removes excessive arguments.
5) Adds `const ELFFile<ELFT> &Obj;` member to `ELFDumper` to simplify the code.

Differential revision: https://reviews.llvm.org/D88097
The file was modifiedllvm/tools/llvm-readobj/ARMEHABIPrinter.h (diff)
The file was modifiedllvm/tools/llvm-readobj/DwarfCFIEHPrinter.h (diff)
The file was modifiedllvm/tools/llvm-readobj/ObjDumper.h (diff)
The file was modifiedllvm/tools/llvm-readobj/llvm-readobj.cpp (diff)
The file was modifiedllvm/tools/llvm-readobj/ObjDumper.cpp (diff)
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp (diff)
Commit ca907bfb57d8ad3ec3bcc2cff2abab7b1b933af6 by sebastian.neubauer
[AMDGPU] Insert waitcnt after returning from call

When memory operations are outstanding on function calls, either the
caller or the callee can insert a waitcnt to ensure that all reads are
finished.
Calls need some time to be executed, so if the callee inserts the
waitcnt, filling the instruction buffer and waiting for memory will be
interleaved, hiding some latency. This comes at the cost of having a
waitcnt inside functions that may not be needed as no memory operations
are outstanding.

For function calls, this is already implemented. The same principal
applies to returns: If the caller inserts a waitcnt after the call, the
callee does not have to wait and the return and memory operation can be
run in parallel.

This commit implements waiting in the caller after returning from a
function call.

Differential Revision: https://reviews.llvm.org/D87674
The file was modifiedllvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/nested-calls.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/store-hi16.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/offset-split-global.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/image_ls_mipmap_zero.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_load_local.ll (diff)
The file was modifiedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/function-returns.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/load-local.96.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/load-hi16.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/call-argument-types.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/wave32.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/store-weird-sizes.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/visit-physreg-vgpr-imm-folding-bug.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/global-saddr-load.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.buffer.ptr.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/shl.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.getlod.dim.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_elt.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/smrd.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/non-entry-alloca.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/imm16.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/call-waitcnt.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx1030.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/load-local.128.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-non-entry-func.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fmax.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/sibling-call.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/offset-split-flat.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/callee-frame-setup.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/infer-uniform-load-shader.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll (diff)
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/call-preserved-registers.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fmin.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_store_local.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/ret_jump.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.ltolz.a16.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/function-args.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/hsa-func.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/memory_clause.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/load-lo16.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.ltolz.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/stack-realign.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fadd.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/mad-mix-hi.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll (diff)
The file was modifiedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected (diff)
Commit d4035af2537432da41b2728829f8cd2fca9a9de8 by grimar
[llvm-readelf/obj] - Print section symbol names properly when dumping relocations.

Currently `--relocations` ignores section symbol names and always prints
section names for them. This is inconsistent with GNU readelf and with `--symbols`.

We have a code in `getFullSymbolName` (which is used for `--symbols`) which can be
reused for `getRelocationTarget` (used for `--relocations`).
With that the issue described is fixed and code becomes a bit shorter.
Also with this change we start to print more relocations (in situations when we just
showed warnings instead before) and also start to report more diagnostic warnings
(see reloc-zero-name-or-value.test).

Differential revision: https://reviews.llvm.org/D87613
The file was modifiedllvm/test/tools/llvm-readobj/ELF/section-symbols.test (diff)
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp (diff)
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/Inputs/compress-debug-sections.yaml (diff)
The file was modifiedllvm/test/tools/llvm-readobj/ELF/relocation-errors.test (diff)
The file was modifiedllvm/test/tools/llvm-readobj/ELF/reloc-zero-name-or-value.test (diff)
Commit bd99fb4e0b5f2f3dcd8c9b81b30b4faebb765001 by grimar
[llvm-readelf/obj] - Fix extended section symbol indices printed in warnings for MIPS GOT/PLT entries.

Recent refactoring introduced a symbol index argument for `getFullSymbolName` method,
which is only used for reporting error messages about invalid extended symbol indexes.

There are few issues in the implementation and we don't report correct symbol indices
when dumping MIPS GOT/PLT entries currently.

This patch adds test cases and fixes the issue.

Differential revision: https://reviews.llvm.org/D88089
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp (diff)
The file was modifiedllvm/test/tools/llvm-readobj/ELF/mips-got.test (diff)
The file was modifiedllvm/test/tools/llvm-readobj/ELF/mips-plt.test (diff)
Commit d0149ba9b46d6ca08b29c9a820b5cb772c799211 by kerry.mclaughlin
[SVE][CodeGen] Lower legal integer -> floating point conversions

This patch adds new ISD nodes, SCVTZ_MERGE_PASSTHRU &
UCVTZ_MERGE_PASSTHRU, which are used to lower both legal
scalable vector [S|U]INT_TO_FP operations and the following intrinsics:
- llvm.aarch64.sve.scvtf
- llvm.aarch64.sve.ucvtf

Reviewed By: sdesmalen, efriedma

Differential Revision: https://reviews.llvm.org/D87913
The file was modifiedllvm/test/CodeGen/AArch64/sve-fcvt.ll (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td (diff)
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp (diff)
Commit bd72ed93d22a1579362859e64a0c7f9c68460cf8 by jperier
[flang] CHARACTER(*) return does not require explicit interface

Fortran 2018 15.4.2.2(4)(c) says nonassumed or explicit non-constant
length parameter require explicit interface. The "nonassumed" part was
missing in f18 characteristic analysis causing CanBeCalledViaImplicitInterface
to return false for `CHARACTER(*) function foo()` like interfaces.

Reviewed By: klausler

Differential Revision: https://reviews.llvm.org/D88075
The file was modifiedflang/lib/Evaluate/characteristics.cpp (diff)
Commit 301e23305d03cfb4004f845a1d9dfdc5e5931fd8 by Yaxun.Liu
[CUDA][HIP] Fix static device var used by host code only

A static device variable may be accessed in host code through
cudaMemCpyFromSymbol etc. Currently clang does not
emit the static device variable if it is only referenced by
host code, which causes host code to fail at run time.

This patch fixes that.

Differential Revision: https://reviews.llvm.org/D88115
The file was modifiedclang/test/CodeGenCUDA/static-device-var-no-rdc.cu (diff)
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp (diff)
Commit 34b08487f04a5a6621d94c17ef49e631cc187f4e by SourabhSingh.Tomar
[OpenMP][flang]Lower NUM_THREADS clause for parallel construct

This patch reflects the work that can be upstreamed from PR(merged)
PR: https://github.com/flang-compiler/f18-llvm-project/pull/411

Reviewed By: jeanPerier

Differential Revision: https://reviews.llvm.org/D87846
The file was modifiedflang/lib/Lower/OpenMP.cpp (diff)
Commit 5711eaf608addccc5a23f0ea00630aa30280ea13 by limo
[mlir] Added support for f64 memref printing in runner utils

Added print_memref_f64 function to runner utils.

Differential Revision: https://reviews.llvm.org/D88143
The file was modifiedmlir/include/mlir/ExecutionEngine/RunnerUtils.h (diff)
The file was modifiedmlir/lib/ExecutionEngine/RunnerUtils.cpp (diff)
Commit be1197c403b22291e35cbc5e96788860ceabd40c by SourabhSingh.Tomar
[flang] Removed OpenMP lowering unittests

These tests aren't adding much value and consensus has been reached for
there removal.
For more context, please refer to discussion in this revision:
https://reviews.llvm.org/D87846
The file was modifiedflang/unittests/CMakeLists.txt (diff)
The file was removedflang/unittests/Lower/OpenMPLoweringTest.cpp
The file was removedflang/unittests/Lower/CMakeLists.txt
Commit dfa9065ad778fe830245e627c7fd9e39f2045bc9 by SourabhSingh.Tomar
[NFCI][flang] Renamed a variable name to a more descriptive name
The file was modifiedflang/lib/Lower/OpenMP.cpp (diff)
Commit c90dee1e90045feb039be640864f038eebd1d8cd by Louis Dionne
[libc++] Re-apply fdc41e11f (LWG1203) without breaking the C++11 build

fdc41e11f was reverted in e46c1def5 because it broke the C++11 build.
We shouldn't be using enable_if_t in C++11, instead we must use
enable_if<...>::type.
The file was modifiedlibcxx/include/ostream (diff)
The file was modifiedlibcxx/include/istream (diff)
The file was addedlibcxx/test/std/input.output/iostream.format/input.streams/istream.rvalue/not_istreamable.verify.cpp
The file was addedlibcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/not_ostreamable.verify.cpp
The file was modifiedlibcxx/www/cxx2a_status.html (diff)
The file was addedlibcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/rvalue.pass.cpp
The file was removedlibcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/CharT_pointer.pass.cpp
The file was modifiedlibcxx/test/std/input.output/iostream.format/input.streams/istream.rvalue/rvalue.pass.cpp (diff)
Commit 20f84257ac4ac54ceb5f581a6081fac6eff2a5a1 by jotrem
[lldb] Fix GetRemoteSharedModule fallback logic

When the various methods of locating the module in GetRemoteSharedModule
fail, make sure we pass the original module spec to the bail-out call to
the provided resolver function.

Also make sure we consistently use the resolved module spec from the
various success paths.

Thanks to what appears to have been an accidentally inverted condition
(commit 85967fa applied the new condition to a path where GetModuleSpec
returns false, but should have applied it when GetModuleSpec returns
true), without this fix we only pass the original module spec in the
fallback if the original spec has no uuid (or has a uuid that somehow
matches the resolved module's uuid despite the call to GetModuleSpec
failing).  This manifested as a bug when processing a minidump file with
a user-provided sysroot, since in that case the resolver call was being
applied to resolved_module_spec (despite resolution failing), which did
not have the path of its file_spec set.

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D88099
The file was modifiedlldb/test/API/functionalities/postmortem/minidump-new/TestMiniDumpNew.py (diff)
The file was modifiedlldb/source/Target/Platform.cpp (diff)
Commit af0207f2bae8578c5283877a786e502ce6e33b14 by Matthew.Arsenault
AMDGPU: Check global FP atomics match default FP mode

We would always select global FP atomics from atomicrmw fadd, although
they have a hardcoded FP mode.
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/global-atomics-fp.ll (diff)
The file was modifiedllvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll (diff)
Commit c463fd136ec259ec269ee6741763ce595811da71 by Matthew.Arsenault
GlobalISel: Fix truncating shift amount in trunc (shl) combine

The shift amount type does not necessarily match the result type. This
was inserting a trunc from s32 to s32, which asserted. Just preserve
the original shift amount type which can be legalized later.
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir (diff)
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shl.mir
Commit 1d1c382ed221f378fc866a524c7c673c239e94bc by aaron
Fix typos in ASTMatchers.h; NFC
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchers.h (diff)
The file was modifiedclang/docs/LibASTMatchersReference.html (diff)

Summary

  1. [zorg] [PowerPC] set lld as the default linker on ppc64le-clang-rhel bot (details)
Commit f6a1fc1366bd977313c9e332c54357b297959d6b by saghir
[zorg] [PowerPC] set lld as the default linker on ppc64le-clang-rhel bot

This patch sets lld as the default linker for ppc64le-clang-rhel-test
buildbot.

Reviewed By: gkistanova

Differential Revision: https://reviews.llvm.org/D87993
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)