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| Change Type | Path in Repository | Path in Workspace |
|---|
 | /llvm/trunk/utils/gn/secondary/llvm/tools/llvm-config/BUILD.gn (diff) | llvm.src/utils/gn/secondary/llvm/tools/llvm-config/BUILD.gn |
Revision
366645
by yuanfang:
[Clang] Replace cc1 options '-mdisable-fp-elim' and '-momit-leaf-frame-pointer' with '-mframe-pointer' After D56351 and D64294, frame pointer handling is migrated to tri-state (all, non-leaf, none) in clang driver and on the function attribute. This patch makes the frame pointer handling cc1 option tri-state. Reviewers: chandlerc, rnk, t.p.northover, MaskRay Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D56353 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /cfe/trunk/include/clang/Basic/CodeGenOptions.def (diff) | clang.src/include/clang/Basic/CodeGenOptions.def |
| /cfe/trunk/include/clang/Basic/CodeGenOptions.h (diff) | clang.src/include/clang/Basic/CodeGenOptions.h |
| /cfe/trunk/include/clang/Driver/CC1Options.td (diff) | clang.src/include/clang/Driver/CC1Options.td |
| /cfe/trunk/include/clang/Driver/Options.td (diff) | clang.src/include/clang/Driver/Options.td |
| /cfe/trunk/lib/CodeGen/CGCall.cpp (diff) | clang.src/lib/CodeGen/CGCall.cpp |
| /cfe/trunk/lib/Driver/ToolChains/Clang.cpp (diff) | clang.src/lib/Driver/ToolChains/Clang.cpp |
| /cfe/trunk/lib/Frontend/CompilerInvocation.cpp (diff) | clang.src/lib/Frontend/CompilerInvocation.cpp |
| /cfe/trunk/test/CodeGen/msp430-fp-elim.c (diff) | clang.src/test/CodeGen/msp430-fp-elim.c |
| /cfe/trunk/test/CodeGen/x86_64-profiling-keep-fp.c (diff) | clang.src/test/CodeGen/x86_64-profiling-keep-fp.c |
| /cfe/trunk/test/CodeGen/xcore-abi.c (diff) | clang.src/test/CodeGen/xcore-abi.c |
| /cfe/trunk/test/CodeGen/xcore-abi.cpp (diff) | clang.src/test/CodeGen/xcore-abi.cpp |
| /cfe/trunk/test/CodeGenCXX/global-init.cpp (diff) | clang.src/test/CodeGenCXX/global-init.cpp |
| /cfe/trunk/test/CodeGenObjCXX/msabi-stret.mm (diff) | clang.src/test/CodeGenObjCXX/msabi-stret.mm |
| /cfe/trunk/test/Driver/cl-options.c (diff) | clang.src/test/Driver/cl-options.c |
| /cfe/trunk/test/Driver/clang-translation.c (diff) | clang.src/test/Driver/clang-translation.c |
| /cfe/trunk/test/Driver/frame-pointer-elim.c (diff) | clang.src/test/Driver/frame-pointer-elim.c |
| /cfe/trunk/test/Driver/frame-pointer.c (diff) | clang.src/test/Driver/frame-pointer.c |
| /cfe/trunk/test/Driver/woa-fp.c (diff) | clang.src/test/Driver/woa-fp.c |
| /cfe/trunk/test/Driver/xcore-opts.c (diff) | clang.src/test/Driver/xcore-opts.c |
Revision
366644
by phosek:
[ELF] Support explicitly overriding relocation model in LTO lld currently selects the relocation model automatically depending on the link flags specified, but in some cases it'd be useful to allow explicitly overriding the relocation model using a flag. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /lld/trunk/Common/TargetOptionsCommandFlags.cpp (diff) | lld.src/Common/TargetOptionsCommandFlags.cpp |
| /lld/trunk/ELF/LTO.cpp (diff) | lld.src/ELF/LTO.cpp |
| /lld/trunk/include/lld/Common/TargetOptionsCommandFlags.h (diff) | lld.src/include/lld/Common/TargetOptionsCommandFlags.h |
| /lld/trunk/test/ELF/lto/relocation-model.ll (diff) | lld.src/test/ELF/lto/relocation-model.ll |
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| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/test/Transforms/InstCombine/2008-12-17-SRemNegConstVec.ll (diff) | llvm.src/test/Transforms/InstCombine/2008-12-17-SRemNegConstVec.ll |
| /llvm/trunk/test/Transforms/InstCombine/2009-06-16-SRemDemandedBits.ll (diff) | llvm.src/test/Transforms/InstCombine/2009-06-16-SRemDemandedBits.ll |
| /llvm/trunk/test/Transforms/InstCombine/2010-01-28-NegativeSRem.ll (diff) | llvm.src/test/Transforms/InstCombine/2010-01-28-NegativeSRem.ll |
| /llvm/trunk/test/Transforms/InstCombine/add4.ll (diff) | llvm.src/test/Transforms/InstCombine/add4.ll |
Revision
366642
by lebedevri:
[NFC][InstCombine] Add srem-by-signbit tests - still can fold to bittest https://rise4fun.com/Alive/IIeS |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/test/Transforms/InstCombine/rem.ll (diff) | llvm.src/test/Transforms/InstCombine/rem.ll |
Revision
366640
by lebedevri:
[NFC][Codegen][X86][AArch64] Add "(x s% C) == 0" tests Much like with `urem`, the same optimization (albeit with slightly different algorithm) applies for the signed case, too. I'm simply copying the test coverage from `urem` case for now, i believe it should be (close to?) sufficient. |
| Change Type | Path in Repository | Path in Workspace |
|---|
 | /llvm/trunk/test/CodeGen/AArch64/srem-seteq-optsize.ll | llvm.src/test/CodeGen/AArch64/srem-seteq-optsize.ll |
| /llvm/trunk/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll | llvm.src/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll |
| /llvm/trunk/test/CodeGen/AArch64/srem-seteq-vec-splat.ll | llvm.src/test/CodeGen/AArch64/srem-seteq-vec-splat.ll |
| /llvm/trunk/test/CodeGen/AArch64/srem-seteq.ll | llvm.src/test/CodeGen/AArch64/srem-seteq.ll |
| /llvm/trunk/test/CodeGen/X86/srem-seteq-optsize.ll | llvm.src/test/CodeGen/X86/srem-seteq-optsize.ll |
| /llvm/trunk/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll | llvm.src/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll |
| /llvm/trunk/test/CodeGen/X86/srem-seteq-vec-splat.ll | llvm.src/test/CodeGen/X86/srem-seteq-vec-splat.ll |
| /llvm/trunk/test/CodeGen/X86/srem-seteq.ll | llvm.src/test/CodeGen/X86/srem-seteq.ll |
Revision
366638
by serge_sans_paille:
Fix asan infinite loop on undefined symbol Fix llvm#39641 Recommit of r366413 Differential Revision: https://reviews.llvm.org/D63877 llvm-svn: 366632 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /compiler-rt/trunk/lib/interception/interception_linux.cc (diff) | compiler-rt.src/lib/interception/interception_linux.cc |
| /compiler-rt/trunk/test/asan/TestCases/Linux/dlopen-mixed-c-cxx.c | compiler-rt.src/test/asan/TestCases/Linux/dlopen-mixed-c-cxx.c |
Revision
366637
by lebedevri:
[Codegen][SelectionDAG] X u% C == 0 fold: non-splat vector improvements Summary: Four things here: 1. Generalize the fold to handle non-splat divisors. Reasonably trivial. 2. Unban power-of-two divisors. I don't see any reason why they should be illegal. * There is no ban in Hacker's Delight * I think the ban came from the same bug that caused the miscompile in the base patch - in `floor((2^W - 1) / D)` we were dividing by `D0` instead of `D`, and we **were** ensuring that `D0` is not `1`, which made sense. 3. Unban `1` divisors. I no longer believe Hacker's Delight actually says that the fold is invalid for `D = 0`. Further considerations: * We know that * `(X u% 1) == 0` can be constant-folded to `1`, * `(X u% 1) != 0` can be constant-folded to `0`, * Also, we know that * `X u<= -1` can be constant-folded to `1`, * `X u> -1` can be constant-folded to `0`, * https://godbolt.org/z/7jnZJX https://rise4fun.com/Alive/oF6p * We know will end up with the following: `(setule/setugt (rotr (mul N, P), K), Q)` * Therefore, for given new DAG nodes and comparison predicates (`ule`/`ugt`), we will still produce the correct answer if: `Q` is a all-ones constant; and both `P` and `K` are *anything* other than `undef`. * The fold will indeed produce `Q = all-ones`. 4. Try to re-splat the `P` and `K` vectors - we don't care about their values for the lanes where divisor was `1`. Reviewers: RKSimon, hermord, craig.topper, spatel, xbolva00 Reviewed By: RKSimon Subscribers: hiraditya, javed.absar, dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63963 |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (diff) | llvm.src/lib/CodeGen/SelectionDAG/TargetLowering.cpp |
| /llvm/trunk/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll (diff) | llvm.src/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll |
| /llvm/trunk/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll (diff) | llvm.src/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll |
Revision
366636
by rksimon:
[X86][SSE] Use PSADBW to improve vXi8 sum reduction (PR42674) As detailed on PR42674, we can reduce a vXi8 down until we have the final <8 x i8>, and then use PSADBW with zero, to sum those values. We then extract the bottom i8, discarding any overflow from the upper bits of the i16 result. |
| Change Type | Path in Repository | Path in Workspace |
|---|
| /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (diff) | llvm.src/lib/Target/X86/X86ISelLowering.cpp |
| /llvm/trunk/test/CodeGen/X86/vector-reduce-add-widen.ll (diff) | llvm.src/test/CodeGen/X86/vector-reduce-add-widen.ll |
| /llvm/trunk/test/CodeGen/X86/vector-reduce-add.ll (diff) | llvm.src/test/CodeGen/X86/vector-reduce-add.ll |
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