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Summary

  1. [PowerPC][NFC] Precomit test case for upcoming patch Just committing a test case for an upcoming patch so that the review can show only the codegen differences.
  2. [X86] SimplifyDemandedVectorEltsForTargetNode - Move SUBV_BROADCAST narrowing handling. NFCI. Move the narrowing of SUBV_BROADCAST to where we handle all the other opcodes.
  3. [PowerPC][NFC] Regenerate test using script This test case ended up as a hybrid of generated checks and manually inserted checks. Regenerate using script to make it consistent.
  4. [InstCombine] Update comment I missed in r366649. NFC
  5. [SmallBitVector] Fix bug in find_next_unset for small types with indices >=32 We were creating a bitmask from a shift of unsigned instead of uintptr_t, meaning we couldn't create masks for indices above 31. Noticed due to a MSVC analyzer warning.
  6. [GISel]: Attach missing range metadata while translating G_LOADs https://reviews.llvm.org/D65048 Attach range information to G_LOAD when only defining one register. reviewed by: arsenm
  7. [ARM] Move MVE VPT block tests into the Thumb2 directory. NFC
Revision 366661 by nemanjai:
[PowerPC][NFC] Precomit test case for upcoming patch

Just committing a test case for an upcoming patch so that the review can show
only the codegen differences.
Change TypePath in RepositoryPath in Workspace
The file was added/llvm/trunk/test/CodeGen/PowerPC/dform-adjust.llllvm.src/test/CodeGen/PowerPC/dform-adjust.ll
Revision 366660 by rksimon:
[X86] SimplifyDemandedVectorEltsForTargetNode - Move SUBV_BROADCAST narrowing handling. NFCI.

Move the narrowing of SUBV_BROADCAST to where we handle all the other opcodes.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (diff)llvm.src/lib/Target/X86/X86ISelLowering.cpp
Revision 366659 by nemanjai:
[PowerPC][NFC] Regenerate test using script

This test case ended up as a hybrid of generated checks and manually inserted
checks. Regenerate using script to make it consistent.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/test/CodeGen/PowerPC/pre-inc-disable.ll (diff)llvm.src/test/CodeGen/PowerPC/pre-inc-disable.ll
Revision 366658 by ctopper:
[InstCombine] Update comment I missed in r366649. NFC
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (diff)llvm.src/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Revision 366657 by rksimon:
[SmallBitVector] Fix bug in find_next_unset for small types with indices >=32

We were creating a bitmask from a shift of unsigned instead of uintptr_t, meaning we couldn't create masks for indices above 31.

Noticed due to a MSVC analyzer warning.
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/include/llvm/ADT/SmallBitVector.h (diff)llvm.src/include/llvm/ADT/SmallBitVector.h
The file was modified/llvm/trunk/unittests/ADT/BitVectorTest.cpp (diff)llvm.src/unittests/ADT/BitVectorTest.cpp
Revision 366656 by aditya_nandakumar:
[GISel]: Attach missing range metadata while translating G_LOADs

https://reviews.llvm.org/D65048

Attach range information to G_LOAD when only defining one register.

reviewed by: arsenm
Change TypePath in RepositoryPath in Workspace
The file was modified/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (diff)llvm.src/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modified/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (diff)llvm.src/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
Revision 366655 by dmgreen:
[ARM] Move MVE VPT block tests into the Thumb2 directory. NFC
Change TypePath in RepositoryPath in Workspace
The file was removed/llvm/trunk/test/CodeGen/ARM/mve-vpt-block.mirllvm.src/test/CodeGen/ARM/mve-vpt-block.mir
The file was removed/llvm/trunk/test/CodeGen/ARM/mve-vpt-block2.mirllvm.src/test/CodeGen/ARM/mve-vpt-block2.mir
The file was removed/llvm/trunk/test/CodeGen/ARM/mve-vpt-block3.mirllvm.src/test/CodeGen/ARM/mve-vpt-block3.mir
The file was removed/llvm/trunk/test/CodeGen/ARM/mve-vpt-block4.mirllvm.src/test/CodeGen/ARM/mve-vpt-block4.mir
The file was removed/llvm/trunk/test/CodeGen/ARM/mve-vpt-block5.mirllvm.src/test/CodeGen/ARM/mve-vpt-block5.mir
The file was removed/llvm/trunk/test/CodeGen/ARM/mve-vpt-block6.mirllvm.src/test/CodeGen/ARM/mve-vpt-block6.mir
The file was added/llvm/trunk/test/CodeGen/Thumb2/mve-vpt-block.mirllvm.src/test/CodeGen/Thumb2/mve-vpt-block.mir
The file was added/llvm/trunk/test/CodeGen/Thumb2/mve-vpt-block2.mirllvm.src/test/CodeGen/Thumb2/mve-vpt-block2.mir
The file was added/llvm/trunk/test/CodeGen/Thumb2/mve-vpt-block3.mirllvm.src/test/CodeGen/Thumb2/mve-vpt-block3.mir
The file was added/llvm/trunk/test/CodeGen/Thumb2/mve-vpt-block4.mirllvm.src/test/CodeGen/Thumb2/mve-vpt-block4.mir
The file was added/llvm/trunk/test/CodeGen/Thumb2/mve-vpt-block5.mirllvm.src/test/CodeGen/Thumb2/mve-vpt-block5.mir
The file was added/llvm/trunk/test/CodeGen/Thumb2/mve-vpt-block6.mirllvm.src/test/CodeGen/Thumb2/mve-vpt-block6.mir