SuccessChanges

Summary

  1. Factor out renaming logic from readability-identifier-naming (details)
  2. [gn build] Port d5c6b8407c1 (details)
  3. [OPENMP]Avoid string concat where possible and use standard name (details)
  4. [IR] fix crash in Constant::isElementWiseEqual() with FP types (details)
  5. [WebAssembly] Track frame registers through VReg and local allocation (details)
  6. Add BuiltinsHexagonDep.def to clang module map (details)
  7. [llvm-nm] Use `StringRef` over `const std::string &` params (details)
  8. AMDGPU: Move permlane discard vdst_in optimization (details)
  9. AMDGPU: Do permlane16 vdst_in discard optimization in InstCombine (details)
  10. Revert "[WebAssembly] Track frame registers through VReg and local (details)
  11. lldb: xfail TestCrossDSOTailCalls.py and TestCrossObjectTailCalls.py on (details)
  12. [libcxx] Temporarily switch back to pthread backend for Fuchsia (details)
  13. [lld][WebAssembly] Use a more meaningful name for stub functions (details)
  14. [mlir] NFC: Fix trivial typos (details)
  15. [mlir] support translation of multidimensional vectors to LLVM IR (details)
  16. [clangd][test] Disable a particular testcase in (details)
  17. AMDGPU: Update clang test (details)
  18. [OPENMP]Do not emit RTTI descriptor for NVPTX devices. (details)
  19. [AArch64][GlobalISel] Change G_FCONSTANTs feeding into stores into (details)
Commit d5c6b8407c12d39a78f42a216369407cb2d7b511 by aaron
Factor out renaming logic from readability-identifier-naming
Before this patch, readability-identifier-naming contained a significant
amount of logic for (a) checking the style of identifiers, followed by
(b) renaming/ applying fix-its. This patch factors out (b) into a
separate base class so that it can be reused by other checks that want
to do renaming. This also cleans up readability-identifier-naming
significantly, since now it only needs to be concerned with the
interesting details of (a).
The file was addedclang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp
The file was modifiedclang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp
The file was modifiedclang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.h
The file was modifiedclang-tools-extra/clang-tidy/utils/CMakeLists.txt
The file was addedclang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.h
Commit cbc63fbdc43b01387b9a604d953cd7627a0a15e2 by llvmgnsyncbot
[gn build] Port d5c6b8407c1
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clang-tidy/utils/BUILD.gn
Commit 8b321929483ee3c4070a10c457733c1bddd10b51 by a.bataev
[OPENMP]Avoid string concat where possible and use standard name
generation function, NFC.
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntime.cpp
Commit 52b44902d059e68c6b5553c1d043f768c516064a by spatel
[IR] fix crash in Constant::isElementWiseEqual() with FP types
We lifted this code from InstCombine for general usage in: rL369842
...but it's not safe as-is. There are no existing users that can trigger
this bug, but I discovered it via crashing several regression tests when
trying to use it for select folding in InstSimplify.
ICmp requires (vector) integer types, so give up on anything that's not
integer or FP (pointers and ?) then bitcast the constants before trying
the match. That matches the definition of "equal or undef" that I was
looking for. If someone wants an FP-aware version of equality (deal with
NaN, -0.0), that could be a different mode or different function.
Differential Revision: https://reviews.llvm.org/D72784
The file was modifiedllvm/unittests/IR/ConstantsTest.cpp
The file was modifiedllvm/lib/IR/Constants.cpp
Commit 3a05c3969c18b5520e360b78fc63cda39a6be98f by dschuff
[WebAssembly] Track frame registers through VReg and local allocation
This change has 2 components:
Target-independent: add a method getDwarfFrameBase to
TargetFrameLowering. It describes how the Dwarf frame base will be
encoded.  That can be a register (the default), the CFA (which replaces
NVPTX-specific logic in DwarfCompileUnit), or a DW_OP_WASM_location
descriptr.
WebAssembly: Allow WebAssemblyFunctionInfo::getFrameRegister to return
the correct virtual register instead of FP32/SP32 after
WebAssemblyReplacePhysRegs has run.  Make WebAssemblyExplicitLocals
store the local it allocates for the frame register. Use this local
information to implement getDwarfFrameBase
The result is that the DW_AT_frame_base attribute is correctly encoded
for each subprogram, and each param and local variable has a correct
DW_AT_location that uses DW_OP_fbreg to refer to the frame base.
Differential Revision: https://reviews.llvm.org/D71681
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/multi-return.ll
The file was modifiedllvm/lib/Target/NVPTX/NVPTXFrameLowering.h
The file was modifiedllvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
The file was modifiedllvm/test/MC/WebAssembly/debug-info.ll
The file was addedllvm/test/MC/WebAssembly/debug-localvar.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.h
The file was modifiedlld/test/wasm/debuginfo.test
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetFrameLowering.h
The file was modifiedllvm/test/MC/WebAssembly/dwarfdump.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp
Commit 202446c639fdd27a54c3be268154a7c66af4f36d by kparzysz
Add BuiltinsHexagonDep.def to clang module map
The file was modifiedclang/include/clang/module.modulemap
Commit fa4112fffc6bd81ba44a9e6ffb19f4314f6e37b0 by sbc
[llvm-nm] Use `StringRef` over `const std::string &` params
Differential Revision: https://reviews.llvm.org/D72718
The file was modifiedllvm/tools/llvm-nm/llvm-nm.cpp
Commit 91e758b7329b4ff134684e661af93a85c436a460 by arsenm2
AMDGPU: Move permlane discard vdst_in optimization
This case can be handled as a regular selection pattern, so move it out
of the weird post-isel folding code which doesn't have an exactly
equivalent place in GlobalISel.
I think it doesn't make much sense to do this optimization here though,
and it would be more useful in instcombine. There's not really any new
information that will be gained during lowering since these inputs were
known from the beginning.
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
Commit 3ef8cdf6660fc20baeb09eae5008b741f178b624 by arsenm2
AMDGPU: Do permlane16 vdst_in discard optimization in InstCombine
There's more potential value to discarding the source value earlier,
since we always know the value of the fi/bc bits.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
Commit 80906d9d16043377ad322c7c44d8a4d3f9914808 by dschuff
Revert "[WebAssembly] Track frame registers through VReg and local
allocation"
This reverts commit 3a05c3969c18b5520e360b78fc63cda39a6be98f. It breaks
under expensive-checks and on Windows
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp
The file was modifiedlld/test/wasm/debuginfo.test
The file was modifiedllvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetFrameLowering.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXFrameLowering.h
The file was modifiedllvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp
The file was modifiedllvm/test/MC/WebAssembly/dwarfdump.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/multi-return.ll
The file was removedllvm/test/MC/WebAssembly/debug-localvar.ll
The file was modifiedllvm/test/MC/WebAssembly/debug-info.ll
Commit 6c4d37733403bf3fda260f1b05fc899427a61cdc by Vedant Kumar
lldb: xfail TestCrossDSOTailCalls.py and TestCrossObjectTailCalls.py on
arm/aarch64
This effectively reverts commit
8d2f252bb8e4d199be8498c4ee2245117ef08fd2, which went a bit too far and
disabled these on all non-Darwin systems.
The file was modifiedlldb/packages/Python/lldbsuite/test/functionalities/tail_call_frames/cross_dso/TestCrossDSOTailCalls.py
The file was modifiedlldb/packages/Python/lldbsuite/test/functionalities/tail_call_frames/cross_object/TestCrossObjectTailCalls.py
Commit 9050d0fb593c60628f47caa122c01ea1dc7a1bf5 by phosek
[libcxx] Temporarily switch back to pthread backend for Fuchsia
We switched to C11 thread API on Fuchsia in ab9aefe, but further testing
showed that Fuchsia's C11 mutex implementation needs a few improvements
for this to be usable, so we temporarily switch back to the pthread
implementation until those issues are addressed.
Differential Revision: https://reviews.llvm.org/D72862
The file was modifiedlibcxx/include/__config
Commit 51b521c07a7a784d087d6a4c176b132cc4e36db7 by sbc
[lld][WebAssembly] Use a more meaningful name for stub functions
When we generate these stub functions on signature mismatches give them
a more meaningful name so that when people see this in stack traces is
gives a clue as the what is going on.
See: https://github.com/emscripten-core/emscripten/issues/10226
Differential Revision: https://reviews.llvm.org/D72881
The file was modifiedlld/wasm/SymbolTable.cpp
The file was modifiedlld/test/wasm/signature-mismatch-export.ll
The file was modifiedlld/test/wasm/signature-mismatch.ll
Commit 73f371c31d2774b3e4d51e4e276737d54922aa18 by zinenko
[mlir] NFC: Fix trivial typos
Summary: Fix trivial typos
Differential Revision: https://reviews.llvm.org/D72672
The file was modifiedmlir/lib/Dialect/GPU/Transforms/MemoryPromotion.cpp
The file was modifiedmlir/include/mlir/Dialect/SPIRV/SPIRVAvailability.td
The file was modifiedmlir/include/mlir/Dialect/SPIRV/SPIRVBase.td
The file was modifiedmlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
The file was modifiedmlir/utils/spirv/define_inst.sh
The file was modifiedmlir/include/mlir/Dialect/VectorOps/VectorOps.td
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVOps.cpp
The file was modifiedmlir/include/mlir/Dialect/SPIRV/SPIRVTypes.h
Commit a4a42160c4463eac74c5d0cfa9a88c4971d8a23e by zinenko
[mlir] support translation of multidimensional vectors to LLVM IR
Summary: MLIR unlike LLVM IR supports multidimensional vector types.
Such types are lowered to nested LLVM IR arrays wrapping an LLVM IR
vector for the innermost dimension of the MLIR vector. MLIR supports
constants of such types using ElementsAttr for values. Introduce support
for converting ElementsAttr into LLVM IR Constant Aggregates
recursively. This enables translation of multidimensional vector
constants from MLIR to LLVM IR.
Differential Revision: https://reviews.llvm.org/D72846
The file was modifiedmlir/test/Target/llvmir.mlir
The file was modifiedmlir/test/Target/llvmir-invalid.mlir
The file was modifiedmlir/lib/Target/LLVMIR/ModuleTranslation.cpp
Commit 42b3c38903c9c80e129ce678db7f522967e91eeb by Jan Korous
[clangd][test] Disable a particular testcase in
FindExplicitReferencesTest when LLVM_ENABLE_EXPENSIVE_CHECKS
The test is failing on our CI bots. Seems like the order of results for
one target is undefined.
(post-commit review) Differential Revision:
https://reviews.llvm.org/D72883
The file was modifiedclang-tools-extra/clangd/unittests/FindTargetTests.cpp
Commit 9b549f26fab6900b5328c0c6239fd77c7527159c by arsenm2
AMDGPU: Update clang test
The file was modifiedclang/test/CodeGenOpenCL/builtins-amdgcn-gfx10.cl
Commit 25b542c61fe364fa86163723b9e35cb7db28bcb4 by a.bataev
[OPENMP]Do not emit RTTI descriptor for NVPTX devices.
Need to disable emission of RTTI descriptors for NVPTX devices to be
able to use dynamic classes without unresolved symbols at link stage.
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedclang/test/OpenMP/nvptx_target_pure_deleted_codegen.cpp
Commit b82d18e1e8e6a997f304cbf591e92af02e067fdb by Jessica Paquette
[AArch64][GlobalISel] Change G_FCONSTANTs feeding into stores into
G_CONSTANTS
Given the following situation:
x = G_FCONSTANT (something that can't be materialized) G_STORE x,
some_addr
We know that x must be materialized as at least a single mov. However,
at the time of selection, the G_STORE will have been regbankselected to
a FPR store.
So, as a result, you'll get an unnecessary fmov into the G_STORE.
Storing a constant value in a GPR and a constant value in a FPR are the
same. So, whenever you see a G_FCONSTANT that feeds into only G_STORES,
so might as well make it a G_CONSTANT.
This adds a target-specific combine which changes G_FCONSTANTs feeding
into G_STOREs into G_CONSTANTs.
Differential Revision: https://reviews.llvm.org/D72814
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was modifiedllvm/lib/Target/AArch64/AArch64PreLegalizerCombiner.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/combine-fconstant.mir