SuccessChanges

Summary

  1. [ScalarizeMaskedMemIntrin] Scalarize constant mask expandload as shuffle(build_vector,pass_through) (details)
  2. [ScalarizeMaskedMemIntrin][X86] Refresh missed transform test cases from rGc0c3b9a25fee (details)
  3. [PowerPC] Add intrinsic to read or set FPSCR register (details)
  4. [SyntaxTree] Implement the List construct. (details)
  5. [LoopInterchange] Form LCSSA phis for values in orig outer loop header. (details)
Commit c0c3b9a25feec84e739cc3a2b30e1ac336648799 by llvm-dev
[ScalarizeMaskedMemIntrin] Scalarize constant mask expandload as shuffle(build_vector,pass_through)

As noticed on D66004, scalarization of an expandload with a constant mask as a chain of irregular loads+inserts makes it tricky to optimize before lowering, resulting in difficulties in merging loads etc.

This patch instead scalarizes the expansion to a build_vector(load0, load1, undef, load2,....) style pattern and then performs a blend shuffle with the pass through vector. This allows us to more easily make use of all the build_vector combines, merging of consecutive loads etc.

Differential Revision: https://reviews.llvm.org/D85416
The file was modifiedllvm/lib/CodeGen/ScalarizeMaskedMemIntrin.cpp
The file was modifiedllvm/test/CodeGen/X86/masked_expandload.ll
Commit 0b26c9eddc4f0112f18f75f64c0fb4e5839a6795 by llvm-dev
[ScalarizeMaskedMemIntrin][X86] Refresh missed transform test cases from rGc0c3b9a25fee

Differential Revision: https://reviews.llvm.org/D85416
The file was modifiedllvm/test/Transforms/ScalarizeMaskedMemIntrin/X86/expand-masked-expandload.ll
Commit dbcfbffc7ae46cc7b84257787681676144a1bd5f by qiucofan
[PowerPC] Add intrinsic to read or set FPSCR register

This patch introduces two intrinsics: llvm.ppc.setflm and
llvm.ppc.readflm. They read from or write to FPSCR register
(floating-point status & control) which contains rounding mode and
exception status.

To ensure correctness of program, we need to prevent FP operations from
being moved across these intrinsics (mffs/mtfsf instruction), so here I
set them as scheduling boundaries. We can relax such restriction if
FPSCR is modeled well in the future.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D84914
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.h
The file was modifiedllvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.cpp
The file was addedllvm/test/CodeGen/PowerPC/read-set-flm.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
Commit a90c78ac52615d256142ecd64fbedabb612dc73f by ecaldas
[SyntaxTree] Implement the List construct.

We defined a List construct to help with the implementation of list-like
grammar rules. This is a first implementation of this API.

Differential Revision: https://reviews.llvm.org/D85295
The file was modifiedclang/include/clang/Tooling/Syntax/Nodes.h
The file was modifiedclang/lib/Tooling/Syntax/Nodes.cpp
The file was modifiedclang/lib/Tooling/Syntax/Tree.cpp
The file was modifiedclang/include/clang/Tooling/Syntax/Tree.h
Commit 54cb552b962097d0e3ef7306b69a3c82cc7fff37 by flo
[LoopInterchange] Form LCSSA phis for values in orig outer loop header.

Values defined in the outer loop header could be used in the inner loop
latch. In that case, we need to create LCSSA phis for them, because after
interchanging they will be defined in the new inner loop and used in the
new outer loop.
The file was modifiedllvm/test/Transforms/LoopInterchange/lcssa-preheader.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopInterchange.cpp