SuccessChanges

Summary

  1. [InstCombine] Regenerate cast tests. NFC. (details)
  2. [X86] Use inlineasm flag output for the _bittest* intrinsics. (details)
  3. [mlir] [VectorOps] Relaxed restrictions on vector.reduction types even more (details)
  4. Revert "Revert "[AArch64][GlobalISel] Add selection support for <8 x s16>  G_INSERT_VECTOR_ELT with GPR scalar."" (details)
  5. [lldb] Add print_function import (details)
  6. Fix a think-o with the numerical suffixes in the docs for init_priority. (details)
  7. [gn build] Re-run CompletionModelCodegen when input json files change (details)
Commit 2f768a68a148a73bf1f52b160a28b9f77c6d830e by llvm-dev
[InstCombine] Regenerate cast tests. NFC.
The file was modifiedllvm/test/Transforms/InstCombine/cast.ll
Commit 288c5776c9d3cb14abe1c86f961c8ff166772d28 by craig.topper
[X86] Use inlineasm flag output for the _bittest* intrinsics.

Instead of expliciting emitting a setc in the inline asm instructions,
we can use flag output. This allows the backend to use the flag
directly if it is needed by a branch. Previously we needed a test
instruction to convert the register back to a flag.

If the flag can't be used directly, the backend will emit a setcc.

Differential Revision: https://reviews.llvm.org/D87888
The file was addedllvm/test/CodeGen/X86/bittest-intrin.ll
The file was modifiedclang/test/CodeGen/bittest-intrin.c
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
Commit e9628955f5e965b0a60b8df3c731fc6bfa87ad20 by ajcbik
[mlir] [VectorOps] Relaxed restrictions on vector.reduction types even more

Recently, restrictions on vector reductions were made more relaxed by
accepting any width signless integer and floating-point. This CL relaxes
the restriction even more by including unsigned and signed integers.

Reviewed By: bkramer

Differential Revision: https://reviews.llvm.org/D88442
The file was addedmlir/integration_test/Dialect/Vector/CPU/test-reductions-si4.mlir
The file was addedmlir/integration_test/Dialect/Vector/CPU/test-reductions-i4.mlir
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
The file was addedmlir/integration_test/Dialect/Vector/CPU/test-reductions-ui4.mlir
Commit 5aa56b242951ab0f0181386ea58509f19b09206e by Amara Emerson
Revert "Revert "[AArch64][GlobalISel] Add selection support for <8 x s16>  G_INSERT_VECTOR_ELT with GPR scalar.""

This isn't a real with the codegen, it's a previously known bug in clang which
causes non-deterministic failures due to garbage bits in undef registers being
used in saturating instructions.

I'm disabling the result checking for the test until this issue is resolved.

This reverts commit 6c8168324b5329c94fe7e8f9a1619802091b9bec.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
Commit 974551d37da8352c22fd849d19cb8fb1facff680 by Jonas Devlieghere
[lldb] Add print_function import
The file was modifiedlldb/docs/conf.py
Commit e7549dafcd33ced4280a81ca1d1ee4cc78ed253f by aaron
Fix a think-o with the numerical suffixes in the docs for init_priority.
The file was modifiedclang/include/clang/Basic/AttrDocs.td
Commit d89735133582ebca482e94bc2710733a09dfb643 by thakis
[gn build] Re-run CompletionModelCodegen when input json files change
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/quality/gen_decision_forest.gni