Commit
9dd83f5ee8697fdb41ba73bc70d845085715b01d
by llvm-dev[DAG] visitVECTOR_SHUFFLE - attempt to match commuted shuffles with MergeInnerShuffle.
Try to match "shuffle(C, shuffle(A, B, M0), M1) -> shuffle(A, B, M2)" etc. by using MergeInnerShuffle's commuted inner shuffle mode.
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 | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (diff) |
 | llvm/test/CodeGen/Thumb2/mve-shuffle.ll (diff) |
 | llvm/test/CodeGen/Thumb2/mve-vld3.ll (diff) |
 | llvm/test/CodeGen/X86/pr34592.ll (diff) |
 | llvm/test/CodeGen/X86/oddshuffles.ll (diff) |
Commit
53dacb7b67758f0c5ea2fe6a3c2030d070017b42
by flo[LV] Generate RT checks up-front and remove them if required.
This patch updates LV to generate the runtime checks just after cost modeling, to allow a more precise estimate of the actual cost of the checks. This information will be used in future patches to generate larger runtime checks in cases where the checks only make up a small fraction of the expected scalar loop execution time.
The runtime checks are created up-front in a temporary block to allow better estimating the cost and un-linked from the existing IR. After deciding to vectorize, the checks are moved backed. If deciding not to vectorize, the temporary block is completely removed.
This patch is similar in spirit to D71053, but explores a different direction: instead of delaying the decision on whether to vectorize in the presence of runtime checks it instead optimistically creates the runtime checks early and discards them later if decided to not vectorize. This has the advantage that the cost-modeling decisions can be kept together and can be done up-front and thus preserving the general code structure. I think delaying (part) of the decision to vectorize would also make the VPlan migration a bit harder.
One potential drawback of this patch is that we speculatively generate IR which we might have to clean up later. However it seems like the code required to do so is quite manageable.
Reviewed By: lebedev.ri, ebrevnov
Differential Revision: https://reviews.llvm.org/D75980
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 | llvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h (diff) |
 | llvm/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll (diff) |
 | llvm/test/Transforms/LoopVectorize/runtime-drop-crash.ll |
 | llvm/test/Transforms/LoopVectorize/pr47343-expander-lcssa-after-cfg-update.ll (diff) |
 | llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll (diff) |
 | llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp (diff) |
 | llvm/lib/Transforms/Vectorize/LoopVectorize.cpp (diff) |
Commit
1b04bdc2f3ffaa7a0e1e3dbdc3a0cd08f0b9a4ce
by ogoffart[SEH] capture 'this'
Simply make sure that the CodeGenFunction::CXXThisValue and CXXABIThisValue are correctly initialized to the recovered value. For lambda capture, we also need to make sure to fill the LambdaCaptureFields
Differential Revision: https://reviews.llvm.org/D97534
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 | clang/test/CodeGenCXX/exceptions-seh-filter-captures.cpp (diff) |
 | clang/lib/CodeGen/CGException.cpp (diff) |
Commit
bd4d4216881d2ddba170808a8cd2f7b75cbc8de9
by fraser[RISCV] Support EXTRACT_SUBVECTOR on vector masks
This patch adds support for extracting subvectors from vector masks. This can be either extracting a scalable vector from another, or a fixed-length vector from a fixed-length or scalable vector.
Since RVV lacks a way to slide vector masks down on an element-wise basis and we don't know the true length of the vector registers, in many cases we must resort to using equivalently-sized i8 vectors to perform the operation. When this is not possible we fall back and extend to a suitable i8 vector.
Support was also added for fixed-length truncation to mask types.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D97475
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 | llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll (diff) |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll (diff) |
 | llvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff) |
Commit
4ea734e6ec9da0587da733424fe616b7e401cf8c
by fraser[RISCV] Unify scalable- and fixed-vector INSERT_SUBVECTOR lowering
This patch unifies the two disparate paths for lowering INSERT_SUBVECTOR operations under one roof. Consequently, with this patch it is possible to support any fixed-length subvector insertion, not just "cast-like" ones.
As before, support for the insertion of mask vectors will come in a separate patch.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D97543
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 | llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (diff) |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll |
 | llvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff) |
Commit
e80ca3af82f8177a1b239bab6bb25d08ec86adeb
by fraser[RISCV] Fix INSERT/EXTRACT_SUBVECTOR on fractional LMUL types
This patch fixes a bug where the lowering for INSERT_SUBVECTOR and EXTRACT_SUBVECTOR would insist on first extracting a register-aligned LMUL1 vector type before perfoming the slide up/down. This was even if the vector was a fractional LMUL type, in which case the aligned EXTRACT_SUBVECTOR was invalid.
This issue only occurred for scalable vector types, but a variety of tests for both scalable and fixed-length vectors have been added to ensure this does not regress in the future.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D97556
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 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll (diff) |
 | llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll (diff) |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll (diff) |
 | llvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff) |
 | llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll (diff) |
Commit
3fea9226eecd2069bea93c4fe5955b0b5ff316f7
by fraser[RISCV] Support INSERT_SUBVECTOR on vector masks
Like with EXTRACT_SUBVECTOR, INSERT_SUBVECTOR poses a problem for vector masks as RVV isn't able to slide mask types around. We choose instead to bitcast to equivalently-sized i8 types where we can, else we zero-extend, perform the operation, and truncate back down.
One test was left disabled due to a crash in the legalizer.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D97559
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 | llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll (diff) |
 | llvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff) |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll (diff) |
Commit
d84440ec919019ac446241db72cfd905c6ac9dfa
by sgueltonUse the default seed value for djb hash for StringMap
See original comment in 560ce2c70fb1fe8e4b9b5e39c54e494a50373ba8 Baiscally the default seed value results in less collision, but changes the iteration order, which matters for a few test cases.
Differential Revision: https://reviews.llvm.org/D97396
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 | llvm/test/DebugInfo/Generic/accel-table-hash-collisions.ll (diff) |
 | llvm/test/DebugInfo/X86/gnu-public-names.ll (diff) |
 | llvm/test/tools/llvm-dwarfdump/X86/section_sizes_macho.test (diff) |
 | llvm/lib/Support/StringMap.cpp (diff) |
 | llvm/test/DebugInfo/Generic/debug-names-hash-collisions.ll (diff) |
 | llvm/test/tools/llvm-dwarfdump/X86/statistics.ll (diff) |
 | llvm/test/DebugInfo/X86/debug-pubtables-dwarf64.ll (diff) |
 | llvm/test/tools/llvm-dwarfdump/X86/section_sizes_elf.test (diff) |