FailedChanges

Summary

  1. Add an assertion to protect against missing Dialect registration in a pass pipeline (NFC) (details)
  2. [SCEV] Attempt to fix windows buildbots (details)
  3. [SelectionDAG] Fix miscompile bug in expandFunnelShift (details)
  4. [NFCI][SimplifyCFG] Combine select costs and checks (details)
  5. Add support for AVR attiny441 and attiny841 (details)
Commit 610706906ae218eaff5b996f64554be7b279e4f0 by joker.eph
Add an assertion to protect against missing Dialect registration in a pass pipeline (NFC)

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D86327
The file was modifiedmlir/lib/Pass/Pass.cpp
The file was modifiedmlir/include/mlir/IR/MLIRContext.h
The file was modifiedmlir/lib/IR/MLIRContext.cpp
The file was modifiedmlir/test/lib/Transforms/TestConvertCallOp.cpp
Commit e286c600e10d06f922e3129bafac640f326cf9ee by sam.parker
[SCEV] Attempt to fix windows buildbots
The file was modifiedllvm/include/llvm/Analysis/ScalarEvolutionExpressions.h
Commit 7a4e26adc8c2c00985fb460aba36a0884d412833 by bjorn.a.pettersson
[SelectionDAG] Fix miscompile bug in expandFunnelShift

This is a fixup of commit 0819a6416fd217 (D77152) which could
result in miscompiles. The miscompile could only happen for targets
where isOperationLegalOrCustom could return different values for
FSHL and FSHR.

The commit mentioned above added logic in expandFunnelShift to
convert between FSHL and FSHR by swapping direction of the
funnel shift. However, that transform is only legal if we know
that the shift count (modulo bitwidth) isn't zero.

Basically, since fshr(-1,0,0)==0 and fshl(-1,0,0)==-1 then doing a
rewrite such as fshr(X,Y,Z) => fshl(X,Y,0-Z) would be incorrect if
Z modulo bitwidth, could be zero.

```
$ ./alive-tv /tmp/test.ll

----------------------------------------
define i32 @src(i32 %x, i32 %y, i32 %z) {
%0:
  %t0 = fshl i32 %x, i32 %y, i32 %z
  ret i32 %t0
}
=>
define i32 @tgt(i32 %x, i32 %y, i32 %z) {
%0:
  %t0 = sub i32 32, %z
  %t1 = fshr i32 %x, i32 %y, i32 %t0
  ret i32 %t1
}
Transformation doesn't verify!
ERROR: Value mismatch

Example:
i32 %x = #x00000000 (0)
i32 %y = #x00000400 (1024)
i32 %z = #x00000000 (0)

Source:
i32 %t0 = #x00000000 (0)

Target:
i32 %t0 = #x00000020 (32)
i32 %t1 = #x00000400 (1024)
Source value: #x00000000 (0)
Target value: #x00000400 (1024)
```

It could be possible to add back the transform, given that logic
is added to check that (Z % BW) can't be zero. Since there were
no test cases proving that such a transform actually would be useful
I decided to simply remove the faulty code in this patch.

Reviewed By: foad, lebedev.ri

Differential Revision: https://reviews.llvm.org/D86430
The file was modifiedllvm/test/CodeGen/AMDGPU/fshl.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit 8ce450da329e3b011ff5adc685ca6eb4c2b09e74 by sam.parker
[NFCI][SimplifyCFG] Combine select costs and checks

Combine the cost modelling and validity checks for the phi to select
conversion in SpeculativelyExecuteBB, extracting the logic out into
a function.
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit 0f0be3fb8ddeca4bbcffc7b22319254c360ca24b by me
Add support for AVR attiny441 and attiny841

Reviewed By: dylanmckay

Differential Revision: https://reviews.llvm.org/D85589

Patch by Julien Etienne
The file was modifiedllvm/lib/Target/AVR/AVRDevices.td