FailedChanges

Summary

  1. [PowerPC] Fix gcc warning [NFC] (details)
  2. [libunwind] Fix warning when building without frameheader cache (details)
  3. [ARM][CGP] Fix scalar condition selects for MVE (details)
  4. [NFC][SimplifyCFG] More tests for Arm (details)
  5. [asan] Also allow for SIGBUS in high-address-dereference.c (details)
  6. Fix crypt.cpp sanitizer test on FreeBSD (details)
  7. Fix update_llc_test_checks function regex for RV64 (details)
  8. [clangd] When inserting "using", add "::" in front if that's the style. (details)
  9. [LV] get.active.lane.mask consuming tripcount instead of backedge-taken count (details)
  10. [libFuzzer] Un-XFAIL msan.test on SystemZ (details)
  11. [compiler-rt][builtins] Add more test cases for __div[sdt]f3 LibCalls (details)
  12. [Utils] Add highlighting definition for byref IR attribute (details)
  13. AMDGPU/GlobalISel: Apply bitcast load/store hack to pointer vectors (details)
  14. [ARM][MVE] Tail-predication: remove the BTC + 1 overflow checks (details)
  15. AMDGPU/GlobalISel: Fix using unlegalizable values in tests (details)
  16. AMDGPU/GlobalISel: Use more accurate legality rules for merge/unmerge (details)
Commit 59e1fbe55784d236d5a9e55b6da592bbbcff9057 by mikael.holmen
[PowerPC] Fix gcc warning [NFC]

Without the fix gcc 7.4 warns with

../lib/Target/PowerPC/PPCAsmPrinter.cpp: In member function 'void {anonymous}::PPCAsmPrinter::EmitTlsCall(const llvm::MachineInstr*, llvm::MCSymbolRefExpr::VariantKind)':
../lib/Target/PowerPC/PPCAsmPrinter.cpp:525:53: warning: enumeral and non-enumeral type in conditional expression [-Wextra]
                  MCInstBuilder(Subtarget->isPPC64() ? Opcode : PPC::BL_TLS)
                                ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Commit 1c39ffecd84a5eba54f5fabb433b0192d1dbd3b4 by mikael.holmen
[libunwind] Fix warning when building without frameheader cache

Without the fix the compiler warns with

/data/repo/master/libunwind/src/AddressSpace.hpp:436:44: warning: unused parameter 'pinfo_size' [-Wunused-parameter]
                                    size_t pinfo_size, void *data) {
                                           ^
1 warning generated.
The file was modifiedlibunwind/src/AddressSpace.hpp
Commit 5b7e27a4db95a07cc140e3980a49a1ee3fb2052c by david.green
[ARM][CGP] Fix scalar condition selects for MVE

The arm backend does not handle select/select_cc on vectors with scalar
conditions, preferring to expand them in codegenprepare instead. This
usually works except when optimizing for size, where the optsize check
would end up overruling the backend isSelectSupported check.

We could handle the selects in ISel too, but this seems like smaller
code than trying to splat the condition to all lanes.

Differential Revision: https://reviews.llvm.org/D86433
The file was addedllvm/test/CodeGen/Thumb2/mve-selectcc.ll
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
Commit ee2fdedd842c373c967494d7b9eb1e8b2b9c7d53 by sam.parker
[NFC][SimplifyCFG] More tests for Arm
The file was modifiedllvm/test/Transforms/SimplifyCFG/ARM/branch-fold-threshold.ll
Commit 5695fa9190595e6c82d14c830060538d227622c9 by Alexander.Richardson
[asan] Also allow for SIGBUS in high-address-dereference.c

FreeBSD delivers a SIGBUS signal for bad addresses rather than SIGSEGV.

Reviewed By: #sanitizers, vitalybuka, yln

Differential Revision: https://reviews.llvm.org/D85409
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_posix.cpp
The file was modifiedcompiler-rt/test/asan/TestCases/Posix/high-address-dereference.c
Commit 39d25064614fb87dcb934739af987c8f66068be2 by Alexander.Richardson
Fix crypt.cpp sanitizer test on FreeBSD

FreeBSD doesn't provide a crypt.h header but instead defines the functions
in unistd.h. Use __has_include() to handle that case.

Reviewed By: #sanitizers, vitalybuka

Differential Revision: https://reviews.llvm.org/D85406
The file was modifiedcompiler-rt/test/sanitizer_common/TestCases/Posix/crypt.cpp
Commit 3221c248d940d6355ad8d0ff35194fd6b87ef87f by Alexander.Richardson
Fix update_llc_test_checks function regex for RV64

Some functions also include a `.Lfunc$local:` label due to
-fno-semantic-interposition

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D85888
The file was modifiedllvm/utils/UpdateTestChecks/asm.py
Commit 4d90ff59ac453a67ac692ffdf8242e4cfbd2b34f by adamcz
[clangd] When inserting "using", add "::" in front if that's the style.

We guess the style based on the existing using declarations. If there
are any and they all start with ::, we add it to the newly added one
too.

Differential Revision: https://reviews.llvm.org/D86473
The file was modifiedclang-tools-extra/clangd/unittests/TweakTests.cpp
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/AddUsing.cpp
Commit ae366479e8c67c18756a823e6ce1c7fcd86a208f by sjoerd.meijer
[LV] get.active.lane.mask consuming tripcount instead of backedge-taken count

This adapts LV to the new semantics of get.active.lane.mask as discussed in
D86147, which means that the LV now emits intrinsic get.active.lane.mask with
the loop tripcount instead of the backedge-taken count as its second argument.
The motivation for this is described in D86147.

Differential Revision: https://reviews.llvm.org/D86304
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
Commit 151f603199669d156e8ff69acca2888f3a8decbc by iii
[libFuzzer] Un-XFAIL msan.test on SystemZ

After https://reviews.llvm.org/D86382 it works.

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D86184
The file was modifiedcompiler-rt/test/fuzzer/msan.test
Commit b9f49d13fd4400274ff24ecd847c710bf0c563c3 by atrosinenko
[compiler-rt][builtins] Add more test cases for __div[sdt]f3 LibCalls

* Make the three tests look more uniformly
* Explicitly specify types of integer and floating point literals
* Add more test cases (mostly inspired by divtf3_test.c)
  - tests are added for obviously special cases such as +/-Inf, +/-0.0 and some
    more implementation-specific cases such as divisor being almost 1.0
* Make NaN in the second test case of `divtf3` to be `sNaN` instead of
  testing for `qNaN` again

Reviewed By: sepavloff

Differential Revision: https://reviews.llvm.org/D84932
The file was modifiedcompiler-rt/test/builtins/Unit/divsf3_test.c
The file was modifiedcompiler-rt/test/builtins/Unit/divdf3_test.c
The file was modifiedcompiler-rt/test/builtins/Unit/fp_test.h
The file was modifiedcompiler-rt/test/builtins/Unit/divtf3_test.c
Commit e1edc1c76dc1efa38b76d42da81f32768e89ba24 by atrosinenko
[Utils] Add highlighting definition for byref IR attribute

This patch assumes `byref` can be handled identically to `byval`.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D85768
The file was modifiedllvm/utils/kate/llvm.xml
The file was modifiedllvm/utils/vim/syntax/llvm.vim
The file was modifiedllvm/utils/vscode/llvm/syntaxes/ll.tmLanguage.yaml
Commit ef8f3b5a78e9653917a5394a978cbc5ce7284a38 by Matthew.Arsenault
AMDGPU/GlobalISel: Apply bitcast load/store hack to pointer vectors

The selection patterns will currently fail on these.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
Commit c352e7fbda2f48c285eca61d2509780f648443ee by sjoerd.meijer
[ARM][MVE] Tail-predication: remove the BTC + 1 overflow checks

This adapts tail-predication to the new semantics of get.active.lane.mask as
defined in D86147. This means that:
- we can remove the BTC + 1 overflow checks because now the loop tripcount is
  passed in to the intrinsic,
- we can immediately use that value to setup a counter for the number of
  elements processed by the loop and don't need to materialize BTC + 1.

Differential Revision: https://reviews.llvm.org/D86303
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/extending-loads.ll
The file was modifiedllvm/lib/Target/ARM/MVETailPredication.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-add-sat.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/basic-tail-pred.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-widen.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-const.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-sub-sat.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-fma-loops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-fabs.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/nested.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-reduce.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-reduce-mve-tail.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/clear-maskedinsts.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
Commit 984a499f9dff0fd16a6d4591970a58fabf966c4c by Matthew.Arsenault
AMDGPU/GlobalISel: Fix using unlegalizable values in tests

Implicit uses of non-register value types places impossible to satisfy
constraints on the legalizer / artifact combiner. These prevent
writing sensible legalize rules for the artifacts without triggering
infinite loops in the legalizer.

The verifier really needs to enforce this, but I'm not sure what the
exact conditions would look like yet.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
Commit 0d2fe90063e956716c3067322aef898822d0dc0e by Matthew.Arsenault
AMDGPU/GlobalISel: Use more accurate legality rules for merge/unmerge

Most notably, we were incorrectly reporting <3 x s16> as a legal type
for these. Make sure these aren't legal to help make progress on
fixing the artifact combiner and vector legalizer
rules. Unfortunately, this means spreading the -global-isel-abort=0
hack, although this doesn't change the legalizer result in any
situation.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir