FailedChanges

Summary

  1. [LiveDebugValues] Add switches for using instr-ref variable locations (details)
  2. [SelectionDAG] Legalize intrinsic get.active.lane.mask (details)
  3. [DWARFYAML] Make the 'Attributes' field optional. (details)
  4. [scudo][standalone] Skip irrelevant regions during release (details)
  5. [Verifier] Additional check for intrinsic get.active.lane.mask (details)
  6. AMDGPU/GlobalISel: re-auto-generate some test checks (details)
  7. [ELF] .note.gnu.property: error for invalid pr_datasize (details)
  8. [InstCombine] add vector demanded elements tests with shuffles; NFC (details)
  9. [InstCombine] improve demanded element analysis for vector insert-of-extract (2nd try) (details)
  10. [LangRef] Revise semantics of intrinsic get.active.lane.mask (details)
  11. [AIX][compiler-rt][builtins] Don't add ppc builtin implementations that require __int128 on AIX (details)
Commit 121a49d839d79f5a72be3e22a9d156c9e4b219dc by jeremy.morse
[LiveDebugValues] Add switches for using instr-ref variable locations

This patch adds the -Xclang option
"-fexperimental-debug-variable-locations" and same LLVM CodeGen option,
to pick which variable location tracking solution to use.

Right now all the switch does is pick which LiveDebugValues
implementation to use, the normal VarLoc one or the instruction
referencing one in rGae6f78824031. Over time, the aim is to add fragments
of support in aid of the value-tracking RFC:

  http://lists.llvm.org/pipermail/llvm-dev/2020-February/139440.html

also controlled by this command line switch. That will slowly move
variable locations to be defined by an instruction calculating a value,
and a DBG_INSTR_REF instruction referring to that value. Thus, this is
going to grow into a "use the new kind of variable locations" switch,
rather than just "use the new LiveDebugValues implementation".

Differential Revision: https://reviews.llvm.org/D83048
The file was addedclang/test/Driver/debug-var-experimental-switch.c
The file was modifiedllvm/lib/CodeGen/CommandFlags.cpp
The file was modifiedllvm/include/llvm/CodeGen/CommandFlags.h
The file was modifiedclang/include/clang/Basic/CodeGenOptions.def
The file was modifiedllvm/include/llvm/Target/TargetOptions.h
The file was modifiedclang/lib/CodeGen/BackendUtil.cpp
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedllvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp
Commit 39522b1e10428e4fa79a9d2dda20cbea7a1168e0 by sjoerd.meijer
[SelectionDAG] Legalize intrinsic get.active.lane.mask

This adapts legalization of intrinsic get.active.lane.mask to the new semantics
as described in D86147. Because the second argument is now the loop tripcount,
we legalize this intrinsic to an 'icmp ULT' instead of an ULE when it was the
backedge-taken count.

Differential Revision: https://reviews.llvm.org/D86302
The file was modifiedllvm/test/CodeGen/Thumb2/active_lane_mask.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Commit 1dc57ada0c79a57fbf7c87d5816e680cfd3bc077 by Xing
[DWARFYAML] Make the 'Attributes' field optional.

This patch makes the 'Attributes' field optional. We don't need to
explicitly specify the 'Attributes' field in the future.

Reviewed By: jhenderson, grimar

Differential Revision: https://reviews.llvm.org/D86537
The file was modifiedllvm/unittests/DebugInfo/DWARF/DWARFDebugInfoTest.cpp
The file was modifiedllvm/lib/ObjectYAML/DWARFYAML.cpp
The file was modifiedllvm/test/tools/yaml2obj/ELF/DWARF/debug-info.yaml
The file was modifiedllvm/test/tools/yaml2obj/ELF/DWARF/debug-abbrev.yaml
Commit bd5ca4f0ed4adfa29150c18a621acb3e71d41450 by kostyak
[scudo][standalone] Skip irrelevant regions during release

With the 'new' way of releasing on 32-bit, we iterate through all the
regions in between `First` and `Last`, which covers regions that do not
belong to the class size we are working with. This is effectively wasted
cycles.

With this change, we add a `SkipRegion` lambda to `releaseFreeMemoryToOS`
that will allow the release function to know when to skip a region.
For the 64-bit primary, since we are only working with 1 region, we never
skip.

Reviewed By: hctim

Differential Revision: https://reviews.llvm.org/D86399
The file was modifiedcompiler-rt/lib/scudo/standalone/release.h
The file was modifiedcompiler-rt/lib/scudo/standalone/primary32.h
The file was modifiedcompiler-rt/lib/scudo/standalone/primary64.h
The file was modifiedcompiler-rt/lib/scudo/standalone/tests/release_test.cpp
Commit 8d5f64c4edbc190a5a8790157fa1d99cfac34016 by sjoerd.meijer
[Verifier] Additional check for intrinsic get.active.lane.mask

This adapts the verifier checks for intrinsic get.active.lane.mask to the new
semantics of it as described in D86147. I.e., the second argument %n, which
corresponds to the loop tripcount, must be greater than 0 if it is a constant,
so check that.

Differential Revision: https://reviews.llvm.org/D86301
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedllvm/test/Verifier/get-active-lane-mask.ll
Commit 8a1926c67aa80d2a9300ab5c90e8cbeb71ba58dc by jay.foad
AMDGPU/GlobalISel: re-auto-generate some test checks
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values-build-vector.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
Commit 25863cc512a38ae9b1235ee62faa79ff2aa3c226 by i
[ELF] .note.gnu.property: error for invalid pr_datasize

A n_type==NT_GNU_PROPERTY_TYPE_0 note encodes a program property.
If pr_datasize is invalid, LLD may crash
(https://github.com/ClangBuiltLinux/linux/issues/1141)

This patch adds some error checking, supports big-endian, and add some tests
for invalid n_descsz.

Differential Revision: https://reviews.llvm.org/D86422
The file was addedlld/test/ELF/gnu-property-err.s
The file was modifiedlld/ELF/InputFiles.cpp
Commit 11f8d4aa104a6fbbf6811d78bd8977954ea59912 by spatel
[InstCombine] add vector demanded elements tests with shuffles; NFC

The 1st draft of D86460 (reverted) would show miscompiles with these tests
because the undef element tracking went wrong and became visible in the
shuffle masks.
The file was modifiedllvm/test/Transforms/InstCombine/vec_demanded_elts.ll
Commit c4f0a0896f23d83952c3dfad9e1e539246d85cb6 by spatel
[InstCombine] improve demanded element analysis for vector insert-of-extract (2nd try)

The 1st attempt (rG557b890) was reverted because it caused miscompiles.
That bug is avoided here by changing the order of folds and as verified
in the new tests.

Original commit message:
InstCombine currently has odd rules for folding insert-extract chains to shuffles,
so we miss collapsing seemingly simple cases as shown in the tests here.

But poison makes this not quite as easy as we might have guessed. Alive2 tests to
show the subtle difference (similar to the regression tests):
https://alive2.llvm.org/ce/z/hp4hv3 (this is ok)
https://alive2.llvm.org/ce/z/ehEWaN (poison leakage)

SLP tends to create these patterns (as shown in the SLP tests), and this could
help with solving PR16739.

Differential Revision: https://reviews.llvm.org/D86460
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/operandorder.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll
The file was modifiedllvm/test/Transforms/InstCombine/vec_demanded_elts.ll
Commit 2002bb487898375d1fc6e43f56e542ecbbce79f8 by sjoerd.meijer
[LangRef] Revise semantics of intrinsic get.active.lane.mask

A first version of get.active.lane.mask was committed in rG7fb8a40e5220. One of
the main purposes and uses of this intrinsic is to communicate information from
the middle-end to the back-end, but its current definition and semantics make
this actually very difficult. The intrinsic was defined as:

  @llvm.get.active.lane.mask(%IV, %BTC)

where %BTC is the Backedge-Taken Count (variable names are different in the
LangRef spec). This allows to implicitly communicate the loop tripcount, which
can be reconstructed by calculating BTC + 1. But it has been very difficult to
prove that calculating BTC + 1 is safe and doesn't overflow. We need
complicated range and SCEV analysis, and thus the problem is that this
intrinsic isn't really doing what it was supposed to solve. Examples of the
overflow checks that are required in the (ARM) back-end are D79175 and D86074,
which aren't even complete/correct yet.

To solve this problem, we are revising the definitions/semantics for
get.active.lane.mask to avoid all the complicated overflow analysis. This means
that instead of communicating the BTC, we are now using the loop tripcount. Now
using LangRef's variable names, its semantics is changed from:

  icmp ule (%base + i), %n

to:

  icmp ult (%base + i), %n

with %n > 0 and corresponding to the loop tripcount. The intrinsic signature
remains the same.

Differential Revision: https://reviews.llvm.org/D86147
The file was modifiedllvm/docs/LangRef.rst
Commit f8454d60b829d6cea4b290a43f2978f0f03f294c by daltenty
[AIX][compiler-rt][builtins] Don't add ppc builtin implementations that require __int128 on AIX

since __int128 currently isn't supported on AIX.

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D85972
The file was modifiedcompiler-rt/lib/builtins/CMakeLists.txt