SuccessChanges

Summary

  1. Allow lit test timeout value to be configurable (details)
Commit f36909d94d45f60fb36b23838e587f5077cf2365 by Azharuddin Mohammed
Allow lit test timeout value to be configurable

Patch by Omar Habra!

Differential Revision: https://reviews.llvm.org/D85173
The file was modifiedtest/jenkins/test_monorepo_build.py (diff)
The file was modifiedzorg/jenkins/monorepo_build.py (diff)

Summary

  1. [LangRef] get.active.lane.mask can produce poison value (details)
  2. [MLIR][Shape] Fix typo (details)
  3. [AMDGPU] Preserve vcc_lo when shrinking V_CNDMASK (details)
  4. Revert "[Verifier] Additional check for intrinsic get.active.lane.mask" (details)
  5. [NFC] Add unittests for findAllocaForValue (details)
  6. [polly][cmake] Don't build LLVMPolly.so without PIC (details)
  7. [DSE,MemorySSA] Traverse use-def chain without MemSSA Walker. (details)
  8. [unittests/Object] - Simplify the code in ELFObjectFileTest.cpp, NFCI. (details)
  9. [ValueTracking] Support select in findAllocaForValue (details)
  10. [lldb] Fix gcc 5.4.0 compile error (details)
  11. [RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move (details)
  12. [RISC-V] Mark C_MV as a move instruction (details)
  13. [RISC-V] fmv.s/fmv.d should be as cheap as a move (details)
  14. [lld][ELF][test] Expand testing of symbols in mergeable sections (details)
  15. Follow up of rGca243b07276a: fixed a typo. NFC. (details)
  16. [AArch64][SVE] Add missing debug info for ACLE types. (details)
  17. [SVE] Fallback to default expansion when lowering SIGN_EXTEN_INREG from non-byte based source. (details)
  18. [NFC][ValueTracking] Fix typo in test (details)
  19. [AArch64] Optimize instruction selection for certain vector shuffles (details)
  20. [NFC][ValueTracking] Cleanup a test (details)
  21. [DSE,MemorySSA] Add test for PR47285. (details)
Commit ca243b07276aec744d86b5f36b475b8b247615aa by sjoerd.meijer
[LangRef] get.active.lane.mask can produce poison value

We had already specified that second argument `n` of this intrinsic is `n > 0`,
but now add to this that the result is a poison value if this is not the case.

Differential Revision: https://reviews.llvm.org/D86637
The file was modifiedllvm/docs/LangRef.rst
Commit 3cb63073ea0f9f0d5efdd22ed08d329d96fb5ae5 by frgossen
[MLIR][Shape] Fix typo

Differential Revision: https://reviews.llvm.org/D86606
The file was modifiedmlir/test/Dialect/Shape/ops.mlir
Commit 4e9d207117f684a7d74132ef10d1c2a2a043b161 by Piotr Sobczak
[AMDGPU] Preserve vcc_lo when shrinking V_CNDMASK

There is no justification for changing vcc_lo to vcc
when shrinking V_CNDMASK, and such a change could
later confuse live variable analysis.

Make sure the original register is preserved.

Differential Revision: https://reviews.llvm.org/D86541
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/shrink-instructions-implicit-vcclo.mir
Commit 1d8af682ef1d1c15c5e8e4341abf18fee0ad238a by sjoerd.meijer
Revert "[Verifier] Additional check for intrinsic get.active.lane.mask"

This reverts commit 8d5f64c4edbc190a5a8790157fa1d99cfac34016.

Thanks to Eli Friedma for pointing out that this check is not appropiate here,
this check will be moved to the Lint pass.
The file was modifiedllvm/test/Verifier/get-active-lane-mask.ll
The file was modifiedllvm/lib/IR/Verifier.cpp
Commit 7f1bb326ee112c5bec897db2be016289f15a7778 by Vitaly Buka
[NFC] Add unittests for findAllocaForValue
The file was modifiedllvm/unittests/Analysis/ValueTrackingTest.cpp
Commit 26d659bbe08028c0e04ddc3f4c698a995f41a131 by ro
[polly][cmake] Don't build LLVMPolly.so without PIC

A build on `sparcv9-sun-solaris2.11` with `-DLLVM_ENABLE_PIC=Off` failed
linking `LLVMPolly.so`:

  [2277/2297] Linking CXX shared module lib/LLVMPolly.so
  FAILED: lib/LLVMPolly.so
  [...]
  ld: fatal: relocation error: R_SPARC_H44: file tools/polly/lib/CMakeFiles/obj.Polly.dir/Analysis/DependenceInfo.cpp.o: symbol .data._ZL16__gthread_active (section): invalid shared object relocation type: ABS44 code model unsupported
  [...]

As on many other targets, one cannot link non-PIC objects into a shared
object on Solaris/sparcv9.

The following patch avoids this by not building the library without PIC.
It allowed the build to finish.

Differential Revision: https://reviews.llvm.org/D85627
The file was modifiedpolly/CMakeLists.txt
The file was modifiedpolly/lib/CMakeLists.txt
The file was modifiedpolly/cmake/CMakeLists.txt
Commit e717fdb0f155deaa03eaae891bd34743e6ffcb64 by flo
[DSE,MemorySSA] Traverse use-def chain without MemSSA Walker.

For DSE with MemorySSA it is beneficial to manually traverse the
defining access, instead of using a MemorySSA walker, so we can
better control the number of steps together with other limits and
also weed out invalid/unprofitable paths early on.

This patch requires a follow-up patch to be most effective, which I will
share soon after putting this patch up.

This temporarily XFAIL's the limit tests, because we now explore more
MemoryDefs that may not alias/clobber the killing def. This will be
improved/fixed by the follow-up patch.

This patch also renames some `Dom*` variables to `Earlier*`, because the
dominance relation is not really used/important here and potentially
confusing.

This patch allows us to aggressively cut down compile time, geomean
-O3 -0.64%, ReleaseThinLTO -1.65%, at the expense of fewer stores
removed. Subsequent patches will increase the number of removed stores
again, while keeping compile-time in check.

http://llvm-compile-time-tracker.com/compare.php?from=d8e3294118a8c5f3f97688a704d5a05b67646012&to=0a929b6978a068af8ddb02d0d4714a2843dd8ba9&stat=instructions

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D86486
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/debug-counter.ll
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-multipath.ll
The file was modifiedllvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/memoryssa-scan-limit.ll
Commit 154901c287c370ef7a2bbe57b034e60c25682bfe by grimar
[unittests/Object] - Simplify the code in ELFObjectFileTest.cpp, NFCI.

This refactors/rewrites the code to remove duplication.

Differential revision: https://reviews.llvm.org/D86623
The file was modifiedllvm/unittests/Object/ELFObjectFileTest.cpp
Commit 469debe0275b5800a2231ae670d235a83e6fbb27 by Vitaly Buka
[ValueTracking] Support select in findAllocaForValue
The file was modifiedllvm/unittests/Analysis/ValueTrackingTest.cpp
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
Commit c1e6f1a7b1a8cb2bb11a76b904c6f8150bfcc3a6 by david.spickett
[lldb] Fix gcc 5.4.0 compile error

Specify type when constructing PromotionKeys,
this fixes error:
"chosen constructor is explicit in copy-initialization"
when compiling lldb with GCC 5.4.0.

This is due to std::tuple having an explicit
default constructor, see:
http://cplusplus.github.io/LWG/lwg-defects.html#2193

Reviewed By: labath

Differential Revision: https://reviews.llvm.org/D86690
The file was modifiedlldb/source/Utility/Scalar.cpp
Commit 2259ce8c9116e2fd057332a1ede08396e8d64d30 by Alexander.Richardson
[RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move

The isTriviallyRematerializable hook is only called for instructions that are
tagged as isAsCheapAsAMove. Since ADDI 0 is used for "mv" it should definitely
be marked with "isAsCheapAsAMove". This change avoids one stack spill in most of
the atomic-rmw.ll tests functions. It also avoids stack spills in two of our
out-of-tree CHERI tests.
ORI/XORI with zero may or may not be the same as a move micro-architecturally,
but since we are already doing it for register == x0, we might as well
do the same if the immediate is zero.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D86480
The file was modifiedllvm/test/CodeGen/RISCV/atomic-rmw.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
The file was modifiedllvm/test/CodeGen/RISCV/vararg.ll
The file was modifiedllvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
Commit a11eeb4d4a99f61c2626ce2c0d44175a9eaa2c59 by Alexander.Richardson
[RISC-V] Mark C_MV as a move instruction

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D86517
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoC.td
Commit 5ba4d0365b36de440d82b4672ccd41a5a7dd4592 by Alexander.Richardson
[RISC-V] fmv.s/fmv.d should be as cheap as a move

Since the canonical floatig-point move is fsgnj rd, rs, rs, we should
handle this case in RISCVInstrInfo::isAsCheapAsAMove().

Reviewed By: lenary

Differential Revision: https://reviews.llvm.org/D86518
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Commit d2385f6d2f1bea4e4913ae3bc3948590e8d9f6c3 by james.henderson
[lld][ELF][test] Expand testing of symbols in mergeable sections

Whilst reviewing some internal testing, I noticed a couple of holes in
coverage of mergeable sections containing symbols. This patch addresses
these holes:
1) Show that mid-piece symbols have their values updated properly when
   pieces are merged.
2) Show the behaviour of symbols in mergeable pieces when --gc-sections
   is enabled.

Reviewed by: grimar, MaskRay

Differential Revision: https://reviews.llvm.org/D86543
The file was addedlld/test/ELF/merge-sym-gc.s
The file was modifiedlld/test/ELF/merge-sym.s
Commit ff6dbb231923de7756f3370fa490aed3ce35787d by sjoerd.meijer
Follow up of rGca243b07276a: fixed a typo. NFC.
The file was modifiedllvm/docs/LangRef.rst
Commit 4e9b66de3f046c1e97b34c938b0920fa6401f40c by sander.desmalen
[AArch64][SVE] Add missing debug info for ACLE types.

This patch adds type information for SVE ACLE vector types,
by describing them as vectors, with a lower bound of 0, and
an upper bound described by a DWARF expression using the
AArch64 Vector Granule register (VG), which contains the
runtime multiple of 64bit granules in an SVE vector.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D86101
The file was addedclang/test/CodeGen/aarch64-debug-sve-vectorx2-types.c
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
The file was addedllvm/test/DebugInfo/AArch64/dbg-sve-types.ll
The file was addedclang/test/CodeGen/aarch64-debug-sve-vectorx3-types.c
The file was addedclang/test/CodeGen/aarch64-debug-sve-vector-types.c
The file was modifiedclang/test/CodeGen/aarch64-sve.c
The file was addedclang/test/CodeGen/aarch64-debug-sve-vectorx4-types.c
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
Commit 81337c915f150f0fbe729a380c7ff32e917859ba by paul.walker
[SVE] Fallback to default expansion when lowering SIGN_EXTEN_INREG from non-byte based source.

Differential Revision: https://reviews.llvm.org/D86394
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
Commit 8191603dc42a1e2631996aae7d24569fbd90c52c by Vitaly Buka
[NFC][ValueTracking] Fix typo in test
The file was modifiedllvm/unittests/Analysis/ValueTrackingTest.cpp
Commit 23d5e93f342e168b59838476abc0e03853609617 by mikhail.maltsev
[AArch64] Optimize instruction selection for certain vector shuffles

This patch adds code to recognize vector shuffles which can be
represented as VDUP (splat) of a vector lane with of a different
(wider) type than the original vector lane type.

For example:
    shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
is essentially:
    shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> <i32 0, i32 0>

Such patterns are generated by the SelectionDAG machinery in some cases
(see DAGCombiner::visitBITCAST in DAGCombiner.cpp, the "Remove double
bitcasts from shuffles" part).

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D86225
The file was modifiedllvm/test/CodeGen/AArch64/neon-extract.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vext_reverse.ll
The file was addedllvm/test/CodeGen/AArch64/neon-wide-splat.ll
The file was modifiedllvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit 6ccacb4680e989b9ef2e9ae9e2a39dafca8d3014 by Vitaly Buka
[NFC][ValueTracking] Cleanup a test
The file was modifiedllvm/unittests/Analysis/ValueTrackingTest.cpp
Commit 73f09ce8f303409a09c7d50d216094ee13d85cab by flo
[DSE,MemorySSA] Add test for PR47285.
The file was addedllvm/test/Transforms/DeadStoreElimination/MSSA/pr47285-not-overwritten-on-all-exit-paths.ll

Summary

  1. Allow lit test timeout value to be configurable (details)
Commit f36909d94d45f60fb36b23838e587f5077cf2365 by Azharuddin Mohammed
Allow lit test timeout value to be configurable

Patch by Omar Habra!

Differential Revision: https://reviews.llvm.org/D85173
The file was modifiedtest/jenkins/test_monorepo_build.py
The file was modifiedzorg/jenkins/monorepo_build.py