FailedChanges

Summary

  1. [LLD][PowerPC] Add a pc-rel based long branch thunk (details)
  2. Reland "[CodeGen][AArch64] Support arm_sve_vector_bits attribute" (details)
  3. [DAGCombine] Don't delete the node if it has uses immediately (details)
  4. [GlobalISel] fix a compilation error with gcc 6.3.0 (details)
  5. [OpenMP] Fixed wrong test command in the test private_mapping.c (details)
  6. [Statepoint] Always spill base pointer. (details)
  7. [PowerPC] Implemented Vector Load with Zero and Signed Extend Builtins (details)
  8. [ARM] Extra gather scatter tailpred test. NFC (details)
  9. [ARM] Correct predicate operand for offset gather/scatter (details)
  10. [libc++] Un-deprecate and un-remove some members of std::allocator (details)
  11. [flang][NFC] Change how error symbols are recorded (details)
Commit bfc76366125b846bfdfac5cc19c356542a399e45 by wei.huang
[LLD][PowerPC] Add a pc-rel based long branch thunk

In this patch, a pc-rel based long branch thunk is added for the local
call protocol that caller and callee does not use TOC.

Reviewed By: sfertile, nemanjai

Differential Revision: https://reviews.llvm.org/D86706
The file was modifiedlld/ELF/Thunks.cpp
The file was addedlld/test/ELF/ppc64-pcrel-long-branch.s
The file was addedlld/test/ELF/ppc64-pcrel-long-branch-error.s
Commit 2ddf795e8cac362e142a82ecea805fdf5daa79b8 by cullen.rhodes
Reland "[CodeGen][AArch64] Support arm_sve_vector_bits attribute"

This relands D85743 with a fix for test
CodeGen/attr-arm-sve-vector-bits-call.c that disables the new pass
manager with '-fno-experimental-new-pass-manager'. Test was failing due
to IR differences with the new pass manager which broke the Fuchsia
builder [1]. Reverted in 2e7041f.

[1] http://lab.llvm.org:8011/builders/fuchsia-x86_64-linux/builds/10375

Original summary:

This patch implements codegen for the 'arm_sve_vector_bits' type
attribute, defined by the Arm C Language Extensions (ACLE) for SVE [1].
The purpose of this attribute is to define vector-length-specific (VLS)
versions of existing vector-length-agnostic (VLA) types.

VLSTs are represented as VectorType in the AST and fixed-length vectors
in the IR everywhere except in function args/return. Implemented in this
patch is codegen support for the following:

  * Implicit casting between VLA <-> VLS types.
  * Coercion of VLS types in function args/return.
  * Mangling of VLS types.

Casting is handled by the CK_BitCast operation, which has been extended
to support the two new vector kinds for fixed-length SVE predicate and
data vectors, where the cast is implemented through memory rather than a
bitcast which is unsupported. Implementing this as a normal bitcast
would require relaxing checks in LLVM to allow bitcasting between
scalable and fixed types. Another option was adding target-specific
intrinsics, although codegen support would need to be added for these
intrinsics. Given this, casting through memory seemed like the best
approach as it's supported today and existing optimisations may remove
unnecessary loads/stores, although there is room for improvement here.

Coercion of VLSTs in function args/return from fixed to scalable is
implemented through the AArch64 ABI in TargetInfo.

The VLA and VLS types are defined by the ACLE to map to the same
machine-level SVE vectors. VLS types are mangled in the same way as:

  __SVE_VLS<typename, unsigned>

where the first argument is the underlying variable-length type and the
second argument is the SVE vector length in bits. For example:

  #if __ARM_FEATURE_SVE_BITS==512
  // Mangled as 9__SVE_VLSIu11__SVInt32_tLj512EE
  typedef svint32_t vec __attribute__((arm_sve_vector_bits(512)));
  // Mangled as 9__SVE_VLSIu10__SVBool_tLj512EE
  typedef svbool_t pred __attribute__((arm_sve_vector_bits(512)));
  #endif

The latest ACLE specification (00bet5) does not contain details of this
mangling scheme, it will be specified in the next revision.  The
mangling scheme is otherwise defined in the appendices to the Procedure
Call Standard for the Arm Architecture, see [2] for more information.

[1] https://developer.arm.com/documentation/100987/latest
[2] https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#appendix-c-mangling

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D85743
The file was addedclang/test/CodeGen/attr-arm-sve-vector-bits-bitcast.c
The file was addedclang/test/CodeGenCXX/aarch64-sve-fixedtypeinfo.cpp
The file was addedclang/test/CodeGenCXX/aarch64-mangle-sve-fixed-vectors.cpp
The file was addedclang/test/CodeGen/attr-arm-sve-vector-bits-types.c
The file was modifiedclang/lib/CodeGen/CGCall.cpp
The file was modifiedclang/lib/CodeGen/CGExprScalar.cpp
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp
The file was modifiedclang/lib/AST/ItaniumMangle.cpp
The file was addedclang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
The file was addedclang/test/CodeGen/attr-arm-sve-vector-bits-call.c
The file was addedclang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
The file was addedclang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
Commit deb4b2580715810ecd5cb7eefa5ffbe65e5eedc8 by Jinsong Ji
[DAGCombine] Don't delete the node if it has uses immediately

This is the follow up patch for https://reviews.llvm.org/D86183 as we miss to delete the node if NegX == NegY, which has use after we create the node.
```
    if (NegX && (CostX <= CostY)) {
      Cost = std::min(CostX, CostZ);
      RemoveDeadNode(NegY);
      return DAG.getNode(Opcode, DL, VT, NegX, Y, NegZ, Flags);  #<-- NegY is used here if NegY == NegX.
    }
```

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D86689
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/fneg.ll
Commit 443d352a1c4c90f3b4f1179f849609a30bd23e62 by yhs
[GlobalISel] fix a compilation error with gcc 6.3.0

With gcc 6.3.0, I hit the following compilation error:
  ../lib/CodeGen/GlobalISel/Combiner.cpp: In member function
      ‘bool llvm::Combiner::combineMachineInstrs(llvm::MachineFunction&,
       llvm::GISelCSEInfo*)’:
  ../lib/CodeGen/GlobalISel/Combiner.cpp:156:54: error: suggest parentheses
       around ‘&&’ within ‘||’ [-Werror=parentheses]
     assert(!CSEInfo || !errorToBool(CSEInfo->verify()) &&
                        ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~
                            "CSEInfo is not consistent. Likely missing calls to "
                            ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                            "observer on mutations");

Fix the code as suggested by the compiler.
The file was modifiedllvm/lib/CodeGen/GlobalISel/Combiner.cpp
Commit 46e0ced762ce2c32bc846b5c0129c3b5020ca5d9 by tianshilei1992
[OpenMP] Fixed wrong test command in the test private_mapping.c

The test command in `private_mapping.c` was set to expect failure by mistake. It is fixed in this patch.

Reviewed By: ABataev

Differential Revision: https://reviews.llvm.org/D86758
The file was modifiedopenmp/libomptarget/test/mapping/private_mapping.c
Commit fabd4c1ae1fc573eb83ba9541e133a265c5549da by dantrushin
[Statepoint] Always spill base pointer.

There is a subtle problem with new statepoint lowering scheme
when base and pointers are the same (see PR46917 for more context):

%1 = STATEPOINT ... %0, %0(tied-def 0)...

if, for some reason, register allocator desides to put two instances
of %0 into two different objects (registers or spill slots), we may
end up with

$reg3 = STATEPOINT ... $reg2, $reg1(tied-def 0)...

and nothing will prevent later passes to sink uses of $reg2 below
statepoint, which is incorrect.

As a short term solution, always put base pointers on stack during
lowering.
A longer term solution may be to rework MIR statepoint format to
avoid GC pointer duplication in statepoint argument list.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D86712
The file was modifiedllvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/statepoint-vreg-details.ll
The file was modifiedllvm/test/CodeGen/X86/statepoint-vreg.ll
Commit 331dcc43eac28b8e659f928fd1f1ce7fd091e1e3 by albionapc
[PowerPC] Implemented Vector Load with Zero and Signed Extend Builtins

This patch implements the builtins for Vector Load with Zero and Signed Extend Builtins (lxvr_x for b, h, w, d), and adds the appropriate test cases for these builtins. The builtins utilize the vector load instructions itnroduced with ISA 3.1.

Differential Revision: https://reviews.llvm.org/D82502#inline-797941
The file was modifiedclang/lib/Headers/altivec.h
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.h
The file was modifiedclang/test/CodeGen/builtins-ppc-p10vector.c
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
Commit 848a7e78413483e32595e8f90dece290fc3fb1ce by david.green
[ARM] Extra gather scatter tailpred test. NFC
The file was modifiedllvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll
Commit 4ca60915bcc87ba318e4fda41fe00da6a04eb671 by david.green
[ARM] Correct predicate operand for offset gather/scatter

These arm_mve_vldr_gather_offset_predicated and
arm_mve_vstr_scatter_offset_predicated have some extra parameters
meaning the predicate is at a later operand. If a loop contains _only_
those masked instructions, we would miss transforming the active lane
mask.

Differential Revision: https://reviews.llvm.org/D86791
The file was modifiedllvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll
The file was modifiedllvm/lib/Target/ARM/MVETailPredication.cpp
Commit 316d336dca7f64f048507f155166daa3821db957 by Louis Dionne
[libc++] Un-deprecate and un-remove some members of std::allocator

This implements the part of P0619R4 related to the default allocator.
This is incredibly important, since otherwise there is an ABI break
between C++17 and C++20 w.r.t. the default allocator's size_type on
platforms where std::size_t is not the same as std::make_unsigned<std::ptrdiff_t>.
The file was addedlibcxx/test/std/utilities/memory/default.allocator/allocator_void.deprecated_in_cxx17.verify.cpp
The file was addedlibcxx/test/std/utilities/memory/default.allocator/allocator_types.removed_in_cxx20.verify.cpp
The file was modifiedlibcxx/include/memory
The file was modifiedlibcxx/test/libcxx/depr/depr.default.allocator/allocator_types.cxx2a.pass.cpp
The file was removedlibcxx/test/libcxx/depr/depr.default.allocator/allocator_types.depr_in_cxx17.verify.cpp
The file was modifiedlibcxx/test/std/utilities/memory/default.allocator/allocator_types.pass.cpp
The file was modifiedlibcxx/test/libcxx/depr/depr.default.allocator/allocator_void.cxx2a.pass.cpp
The file was removedlibcxx/test/libcxx/depr/depr.default.allocator/allocator_void.depr_in_cxx17.verify.cpp
The file was modifiedlibcxx/www/cxx1z_status.html
The file was addedlibcxx/test/std/utilities/memory/default.allocator/allocator_types.deprecated_in_cxx17.verify.cpp
The file was modifiedlibcxx/www/cxx2a_status.html
Commit 627e9007eaba39624fe92a4d97dceb18bc51f190 by tkeith
[flang][NFC] Change how error symbols are recorded

When an error is associated with a symbol, it was marked with a flag
from Symbol::Flag. The problem with that is that you need a mutable
symbol to do that. Instead, store the set of error symbols in the
SemanticsContext. This allows for some const_casts to be eliminated.

Also, improve the internal error that occurs if SetError is called
but no fatal error has been reported.

Differential Revision: https://reviews.llvm.org/D86740
The file was modifiedflang/include/flang/Semantics/type.h
The file was modifiedflang/include/flang/Semantics/semantics.h
The file was modifiedflang/lib/Semantics/semantics.cpp
The file was modifiedflang/lib/Semantics/type.cpp
The file was modifiedflang/include/flang/Semantics/symbol.h
The file was modifiedflang/lib/Semantics/expression.cpp
The file was modifiedflang/lib/Semantics/tools.cpp
The file was modifiedflang/lib/Semantics/resolve-names.cpp