SuccessChanges

Summary

  1. [InstCombine] adjust recip sqrt tests for better coverage; NFC (details)
  2. [llvm-readobj] - Remove Error.cpp,.h and drop dependencies in the code. (details)
  3. [NFC] Test commit, whitespace changes (details)
  4. [LoopIdiomRecognizePass] Options to disable part or the entire Loop Idiom Recognize Pass (details)
  5. [SystemZ][z/OS] Adding initial toolchain for z/OS (details)
  6. [SystemZ][z/OS] Fix build break in z/OS toolchain (details)
  7. AMDGPU: Convert test to MIR (details)
  8. AMDGPU: Check some offsets in test (details)
  9. PowerPC: Switch test to generated checks (details)
  10. GlobalISel: Artifact combine unmerge of unmerge (details)
  11. Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain" (details)
  12. GlobalISel: Implement computeKnownBits for G_UNMERGE_VALUES (details)
  13. GlobalISel: Implement computeNumSignBits for G_SEXTLOAD/G_ZEXTLOAD (details)
Commit d48699e3e89f342ecb9dfc288f6840cd41ecb5e5 by spatel
[InstCombine] adjust recip sqrt tests for better coverage; NFC

Goes with D86726
The file was modifiedllvm/test/Transforms/InstCombine/fmul-sqrt.ll
Commit 3d90a61cf2edc22f1f006de351a1812592a7648b by grimar
[llvm-readobj] - Remove Error.cpp,.h and drop dependencies in the code.

We have Error.cpp/.h which contains some code for working with error codes.
In fact we use Error/Expected<> almost everywhere already and we can get rid
of these files.

Note: a few places in the code used readobj specific error codes,
e.g. `return readobj_error::unknown_symbol`. But these codes are never really used,
i.e. the code checks the fact of a success/error call only.
So I've changes them to `return inconvertibleErrorCode()` for now.
It seems that these places probably should be converted to use `Error`/`Expected<>`.

Differential revision: https://reviews.llvm.org/D86772
The file was modifiedllvm/tools/llvm-readobj/ARMEHABIPrinter.h
The file was modifiedllvm/tools/llvm-readobj/llvm-readobj.cpp
The file was modifiedllvm/tools/llvm-readobj/COFFDumper.cpp
The file was modifiedllvm/tools/llvm-readobj/ObjDumper.cpp
The file was removedllvm/tools/llvm-readobj/Error.cpp
The file was modifiedllvm/tools/llvm-readobj/WindowsResourceDumper.cpp
The file was modifiedllvm/tools/llvm-readobj/XCOFFDumper.cpp
The file was modifiedllvm/test/tools/llvm-readobj/archive.test
The file was modifiedllvm/tools/llvm-readobj/Win64EHDumper.cpp
The file was modifiedllvm/tools/llvm-readobj/CMakeLists.txt
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedllvm/tools/llvm-readobj/WasmDumper.cpp
The file was removedllvm/tools/llvm-readobj/Error.h
The file was modifiedllvm/tools/llvm-readobj/MachODumper.cpp
The file was modifiedllvm/tools/llvm-readobj/DwarfCFIEHPrinter.h
The file was modifiedllvm/tools/llvm-readobj/ARMWinEHPrinter.cpp
Commit 5a3ede58e2c1df53cf1f74d2b8c4916c4a974b0b by Abhina.Sreeskantharajan
[NFC] Test commit, whitespace changes

Differential Revision: https://reviews.llvm.org/D85324
The file was modifiedclang/test/Preprocessor/init-zos.c
Commit 68717acb24e505169509b590e8c83557da54451e by anhtuyen
[LoopIdiomRecognizePass] Options to disable part or the entire Loop Idiom Recognize Pass

Loop Idiom Recognize Pass (LIRP) attempts to transform loops with subscripted arrays
into memcpy/memset function calls. In some particular situation, this transformation
introduces negative impacts. For example: https://bugs.llvm.org/show_bug.cgi?id=47300

This patch will enable users to disable a particular part of the transformation, while
he/she can still enjoy the benefit brought about by the rest of LIRP. The default
behavior stays unchanged: no part of LIRP is disabled by default.

Reviewed By: etiotto (Ettore Tiotto)

Differential Revision: https://reviews.llvm.org/D86262
The file was modifiedllvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
The file was modifiedllvm/include/llvm/Transforms/Scalar/LoopIdiomRecognize.h
The file was addedllvm/test/Transforms/LoopIdiom/disable-options.ll
Commit 3e1e5f54492d5bdebd40388247254e310cf62c3d by Abhina.Sreeskantharajan
[SystemZ][z/OS] Adding initial toolchain for z/OS

This patch adds the initial toolchain for z/OS that will set some defaults. In subsequent patches, we plan to add support to use the system linker and assembler.

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D86707
The file was modifiedclang/lib/Driver/Driver.cpp
The file was addedclang/lib/Driver/ToolChains/ZOS.cpp
The file was modifiedclang/lib/Driver/CMakeLists.txt
The file was addedclang/lib/Driver/ToolChains/ZOS.h
Commit c831a14aa16a74fa94c94a351a4bc7812a8bd166 by Abhina.Sreeskantharajan
[SystemZ][z/OS] Fix build break in z/OS toolchain

Differential Revision: https://reviews.llvm.org/D86707
The file was modifiedclang/lib/Driver/ToolChains/ZOS.cpp
Commit 4a9a4885aef9529788cc32999f998254a3730179 by Matthew.Arsenault
AMDGPU: Convert test to MIR

Currently the dbg_value ends up in the relaxed branch block. A future
commit will push the dbg_value out of this block, and I'm not sure how
to coax the IR into producing the same MIR at the relevant point.
The file was removedllvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.ll
The file was addedllvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir
Commit 7f5b4eaae4892539f2c4c1e32c61b297363c7341 by Matthew.Arsenault
AMDGPU: Check some offsets in test

This will make updating the checks easier in a future change.
The file was modifiedllvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
Commit 0f42d185346a5c383cf4d30e02c68b39440ed9dd by Matthew.Arsenault
PowerPC: Switch test to generated checks
The file was modifiedllvm/test/CodeGen/PowerPC/vsx-args.ll
The file was modifiedllvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll
Commit 18bbd9f15eb031c5c7e58ebe0692f87fa8d5954f by Matthew.Arsenault
GlobalISel: Artifact combine unmerge of unmerge

Unmerges have the same fundamental problem as G_TRUNC, and G_TRUNC
could be implemented in terms of G_UNMERGE_VALUES. Reducing the number
of elements in unmerge results ends up producing the original unmerge
type profile, so the artifact combiner needs to eliminate the
intermediate illegal registers. This avoids infinite looping in the
legalizer in a future change.

Assuming an unmerge has each result unmerged the same way, this ends
up producing a new unmerge of the source for every definition. I'm not
sure if the artifact combiner should either insert temporary merges
here and erase the original merge, or if the combiner should look at
uses from defs rather than defs from uses for unmerges.

In a few cases this regresses from using 16-bit shifts for 8-bit
values to using 32-bit shifts, but I think these can be legalized
later (the other legalization rules don't try very hard to use 16-bit
shifts either).
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
The file was modifiedllvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
Commit bc9a29b9ee6ade4894252b1470977142c32b4602 by paul.walker
Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain"

This reverts commit e9d9a612084b47fc4277523561d61e675370c854.

This patch was previously revert by 04879086b44348cad600a0a1ccbe1f7776cc3cf9
with the reapplication being done after breaking the assert used to
ensure SP is always 16-byte aligned, which is a requirement of the AAPCS.

For extra context the latest patch caused runtime failures when
building with "-march=armv8-a+sve -mllvm -aarch64-sve-vector-bits-min=256".
The file was removedllvm/test/CodeGen/AArch64/framelayout-fp-csr.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
The file was removedllvm/test/CodeGen/AArch64/framelayout-unaligned-fp.ll
The file was removedllvm/test/CodeGen/AArch64/framelayout-frame-record.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
Commit 92090e8bd80179ec780bb67e1e7d95eceefbdd56 by Matthew.Arsenault
GlobalISel: Implement computeKnownBits for G_UNMERGE_VALUES
The file was modifiedllvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
The file was modifiedllvm/include/llvm/Support/KnownBits.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
Commit 9e7e1b2d4b13d0abb1e34feedfc004ae2b2dab3a by Matthew.Arsenault
GlobalISel: Implement computeNumSignBits for G_SEXTLOAD/G_ZEXTLOAD
The file was modifiedllvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir