FailedChanges

Summary

  1. [X86][SSE] Don't use LowerVSETCCWithSUBUS for unsigned compare with +ve operands (PR47448) (details)
  2. [Sparc] Add reduced funnel shift test case for PR47303 (details)
  3. AntiDepBreaker.h - remove unnecessary ScheduleDAG.h include. NFCI. (details)
  4. [flang] Fix link to old repo location in doxygen mainpage. NFC. (details)
  5. [analyzer][StdLibraryFunctionsChecker] Add POSIX pthread handling functions (details)
  6. [flang] Spelling and format edits to README.txt. NFC. (details)
  7. [analyzer][StdLibraryFunctionsChecker] Have proper weak dependencies (details)
  8. Reduce the number of memory allocations when displaying (details)
  9. [AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block (details)
  10. [InstCombine] move/add tests for icmp with mul operands; NFC (details)
  11. [InstCombine] improve folds for icmp with multiply operands (PR47432) (details)
Commit 9de0a3da6a76030f96a2d6793ca4f094fa538db5 by llvm-dev
[X86][SSE] Don't use LowerVSETCCWithSUBUS for unsigned compare with +ve operands (PR47448)

We already simplify the unsigned comparisons if we've found the operands are non-negative, but we were still calling LowerVSETCCWithSUBUS which resulted in the PR47448 regressions.
The file was modifiedllvm/test/CodeGen/X86/vector-unsigned-cmp.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit c4056f842827db97e9861ae92360202aa0863199 by llvm-dev
[Sparc] Add reduced funnel shift test case for PR47303
The file was addedllvm/test/CodeGen/SPARC/fshl.ll
Commit 783d7116dc8b739263125c607ec034f9d580291e by llvm-dev
AntiDepBreaker.h - remove unnecessary ScheduleDAG.h include. NFCI.
The file was modifiedllvm/include/llvm/CodeGen/AntiDepBreaker.h
Commit 2e1827271cb1c090cced7369282f9edcf9e59183 by richard.barton
[flang] Fix link to old repo location in doxygen mainpage. NFC.
The file was modifiedflang/docs/doxygen-mainpage.dox
Commit d01280587d97eb02d37da37666afd3e4d57c9336 by gabor.marton
[analyzer][StdLibraryFunctionsChecker] Add POSIX pthread handling functions

Differential Revision: https://reviews.llvm.org/D84415
The file was modifiedclang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
The file was modifiedclang/test/Analysis/std-c-library-functions-POSIX.c
Commit 7e5dab5fca4b154f12d3a313a6bdbd507f2314be by richard.barton
[flang] Spelling and format edits to README.txt. NFC.
The file was modifiedflang/README.md
Commit 8248c2af94975912b14e7e0cb414fcbb82c77123 by gabor.marton
[analyzer][StdLibraryFunctionsChecker] Have proper weak dependencies

We want the generice StdLibraryFunctionsChecker to report only if there
are no specific checkers that would handle the argument constraint for a
function.

Note, the assumptions are still evaluated, even if the arguement
constraint checker is set to not report. This means that the assumptions
made in the generic StdLibraryFunctionsChecker should be an
over-approximation of the assumptions made in the specific checkers. But
most importantly, the assumptions should not contradict.

Differential Revision: https://reviews.llvm.org/D87240
The file was addedclang/test/Analysis/std-c-library-functions-arg-weakdeps.c
The file was modifiedclang/include/clang/StaticAnalyzer/Checkers/Checkers.td
The file was addedclang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c
The file was modifiedclang/test/Analysis/analyzer-enabled-checkers.c
Commit eb482afaf5bbf3abf9d02c3810e418945c68a936 by momchil.velikov
Reduce the number of memory allocations when displaying
a warning about clobbering reserved registers (NFC).

Also address some minor inefficiencies and style issues.

Differential Revision: https://reviews.llvm.org/D86088
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
Commit 2480a31e5d69a5c2e8e900be3a7f706d77f5a5cc by Alexander Timofeev
[AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block

optimizeEndCF removes EXEC restoring instruction case this instruction is the only one except the branch to the single successor and that successor contains EXEC mask restoring instruction that was lowered from END_CF belonging to IF_ELSE.
As a result of such optimization we get the basic block with the only one instruction that is a branch to the single successor.
In case the control flow can reach such an empty block from S_CBRANCH_EXEZ/EXECNZ it might happen that spill/reload instructions that were inserted later by register allocator are placed under exec == 0 condition and never execute.
Removing empty block solves the problem.

This change require further work to re-implement LIS updates. Recently, LIS is always nullptr in this pass. To enable it we need another patch to fix many places across the codegen.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D86634
The file was modifiedllvm/test/CodeGen/AMDGPU/collapse-endcf.mir
The file was modifiedllvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
Commit 11d8eedfa5b796a9ba0276a5e4bad8b9e549f0b6 by spatel
[InstCombine] move/add tests for icmp with mul operands; NFC
The file was modifiedllvm/test/Transforms/InstCombine/icmp-mul.ll
The file was modifiedllvm/test/Transforms/InstCombine/icmp.ll
Commit 7a6d6f0f7046f6ebcbf06eaf8f996d991a90e440 by spatel
[InstCombine] improve folds for icmp with multiply operands (PR47432)

Check for no overflow along with an odd constant before
we lose information by converting to bitwise logic.

https://rise4fun.com/Alive/2Xl

  Pre: C1 != 0
  %mx = mul nsw i8 %x, C1
  %my = mul nsw i8 %y, C1
  %r = icmp eq i8 %mx, %my
  =>
  %r = icmp eq i8 %x, %y

  Name: nuw ne
  Pre: C1 != 0
  %mx = mul nuw i8 %x, C1
  %my = mul nuw i8 %y, C1
  %r = icmp ne i8 %mx, %my
  =>
  %r = icmp ne i8 %x, %y

  Name: odd ne
  Pre: C1 % 2 != 0
  %mx = mul i8 %x, C1
  %my = mul i8 %y, C1
  %r = icmp ne i8 %mx, %my
  =>
  %r = icmp ne i8 %x, %y
The file was modifiedllvm/test/Transforms/InstCombine/icmp-mul.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp