SuccessChanges

Summary

  1. [libc++] Make sure we always print all available features (details)
  2. [libc++] Allow overriding the cached value of LIBCXX_TEST_CONFIG (details)
  3. [clang-format] Handle shifts within conditions (details)
  4. [AMDGPU] Support disassembly for AMDGPU kernel descriptors (details)
  5. [clang-tidy] Fix linking for FrontendOpenMP (details)
  6. Add an option for unrolling loops up to a factor. (details)
  7. LiveRegUnits.h - reduce MachineRegisterInfo.h include. NFC. (details)
  8. [WebAssembly] Fix fixEndsAtEndOfFunction for try-catch (details)
  9. GlobalISel: Combine `op undef, x` to 0 (details)
  10. [ARM] Follow AACPS standard for volatile bit-fields access width (details)
  11. [GVN] Add testcase that uses masked loads and stores, NFC (details)
  12. Add more explicit error message when creating a type or attribute for an unregistered dialect (NFC) (details)
Commit 6454140ab34cb29cc0b9de4f1e80199d717f1a97 by Louis Dionne
[libc++] Make sure we always print all available features

Previously, we'd only print the features added through the new config,
however printing all the features is important for debugging purposes.
The file was modifiedlibcxx/utils/libcxx/test/config.py
Commit c2f6a0012882ba9b39ccee53f3d7f4f1aedf2181 by Louis Dionne
[libc++] Allow overriding the cached value of LIBCXX_TEST_CONFIG
The file was modifiedlibcxx/CMakeLists.txt
Commit c81dd3d159ab03d46e4280c458d3c29e56648218 by mydeveloperday
[clang-format] Handle shifts within conditions

In some situation shifts can be treated as a template, and is thus formatted as one. So, by doing a couple extra checks to assure that the condition doesn't contain a template, and is in fact a bit shift should solve this problem.

This is a fix for [[ https://bugs.llvm.org/show_bug.cgi?id=46969 | bug 46969 ]]

Reviewed By: MyDeveloperDay

Patch By: Saldivarcher

Differential Revision: https://reviews.llvm.org/D86581
The file was modifiedclang/lib/Format/TokenAnnotator.cpp
The file was modifiedclang/unittests/Format/FormatTest.cpp
Commit 487a80531006add8102d50dbcce4b6fd729ab1f6 by RonakNilesh.Chauhan
[AMDGPU] Support disassembly for AMDGPU kernel descriptors

Decode AMDGPU Kernel descriptors as assembler directives.

Reviewed By: scott.linder, jhenderson, kzhuravl

Differential Revision: https://reviews.llvm.org/D80713
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.cpp
The file was modifiedllvm/include/llvm/Support/AMDHSAKernelDescriptor.h
The file was modifiedllvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/nop-data.ll
The file was addedllvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s
The file was addedllvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx9.s
The file was addedllvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-failure.s
The file was addedllvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-sgpr.s
The file was addedllvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-vgpr.s
The file was modifiedllvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
The file was addedllvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-raw.s
Commit 71133e8b5bceaf68a2cee59af371df570a1aed79 by aheejin
[clang-tidy] Fix linking for FrontendOpenMP

Without this, builds with `-DBUILD_SHARED_LIBS=ON` fail.
The file was modifiedclang-tools-extra/clang-tidy/altera/CMakeLists.txt
Commit e2394245eb28695d5eed5d7c015e99141993c723 by Lubomir.Litchev
Add an option for unrolling loops up to a factor.

Currently, there is no option to allow for unrolling a loop up to a specific factor (specified by the user).
The code for doing that is there and there are benefits when unrolling is done  to smaller loops (smaller than the factor specified).

Reviewed By: bondhugula

Differential Revision: https://reviews.llvm.org/D87111
The file was modifiedmlir/lib/Transforms/Utils/LoopUtils.cpp
The file was modifiedmlir/test/lib/Transforms/TestLoopUnrolling.cpp
The file was modifiedmlir/lib/Dialect/Affine/Transforms/LoopUnroll.cpp
The file was modifiedmlir/include/mlir/Dialect/Affine/Passes.h
The file was modifiedmlir/test/Dialect/SCF/loop-unroll.mlir
The file was modifiedmlir/include/mlir/Dialect/Affine/Passes.td
Commit 3c83b967cf223ce6a2e0813e48b64f7689512f20 by llvm-dev
LiveRegUnits.h - reduce MachineRegisterInfo.h include. NFC.

We only need to include MachineInstrBundle.h, but exposes an implicit dependency in MachineOutliner.h.

Also, remove duplicate includes from LiveRegUnits.cpp + MachineOutliner.cpp.
The file was modifiedllvm/include/llvm/CodeGen/LiveRegUnits.h
The file was modifiedllvm/lib/CodeGen/LiveRegUnits.cpp
The file was modifiedllvm/lib/CodeGen/MachineOutliner.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineOutliner.h
Commit d25c17f3175b344420c1f30040b206a47a512c9d by aheejin
[WebAssembly] Fix fixEndsAtEndOfFunction for try-catch

When the function return type is non-void and `end` instructions are at
the very end of a function, CFGStackify's `fixEndsAtEndOfFunction`
function fixes the corresponding block/loop/try's type to match the
function's return type. This is applied to consecutive `end` markers at
the end of a function. For example, when the function return type is
`i32`,
```
block i32    ;; return type is fixed to i32
  ...
  loop i32   ;; return type is fixed to i32
    ...
  end_loop
end_block
end_function
```

But try-catch is a little different, because it consists of two parts:
a try part and a catch part, and both parts' return type should satisfy
the function's return type. Which means,
```
try i32      ;; return type is fixed to i32
  ...
  block i32  ;; this should be changed i32 too!
    ...
  end_block
catch
  ...
end_try
end_function
```
As you can see in this example, it is not sufficient to only `end`
instructions at the end of a function; in case of `try`, we should
check instructions before `catch`es, in case their corresponding `try`'s
type has been fixed.

This changes `fixEndsAtEndOfFunction`'s algorithm to use a worklist
that contains a reverse iterator, each of which is a starting point for
a new backward `end` instruction search.

Fixes https://bugs.llvm.org/show_bug.cgi?id=47413.

Reviewed By: dschuff, tlively

Differential Revision: https://reviews.llvm.org/D87207
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll
Commit 1242dd330d9054a57c1403f16d5487f9e3a3a92f by vkeles
GlobalISel: Combine `op undef, x` to 0

https://reviews.llvm.org/D86611
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/combine-shl.mir
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
Commit 514df1b2bb1ecd1a33327001ea38a347fd2d0380 by ties.stuij
[ARM] Follow AACPS standard for volatile bit-fields access width

This patch resumes the work of D16586.
According to the AAPCS, volatile bit-fields should
be accessed using containers of the widht of their
declarative type. In such case:
```
struct S1 {
  short a : 1;
}
```
should be accessed using load and stores of the width
(sizeof(short)), where now the compiler does only load
the minimum required width (char in this case).
However, as discussed in D16586,
that could overwrite non-volatile bit-fields, which
conflicted with C and C++ object models by creating
data race conditions that are not part of the bit-field,
e.g.
```
struct S2 {
  short a;
  int  b : 16;
}
```
Accessing `S2.b` would also access `S2.a`.

The AAPCS Release 2020Q2
(https://documentation-service.arm.com/static/5efb7fbedbdee951c1ccf186?token=)
section 8.1 Data Types, page 36, "Volatile bit-fields -
preserving number and width of container accesses" has been
updated to avoid conflict with the C++ Memory Model.
Now it reads in the note:
```
This ABI does not place any restrictions on the access widths of bit-fields where the container
overlaps with a non-bit-field member or where the container overlaps with any zero length bit-field
placed between two other bit-fields. This is because the C/C++ memory model defines these as being
separate memory locations, which can be accessed by two threads simultaneously. For this reason,
compilers must be permitted to use a narrower memory access width (including splitting the access into
multiple instructions) to avoid writing to a different memory location. For example, in
struct S { int a:24; char b; }; a write to a must not also write to the location occupied by b, this requires at least two
memory accesses in all current Arm architectures. In the same way, in struct S { int a:24; int:0; int b:8; };,
writes to a or b must not overwrite each other.
```

Patch D16586 was updated to follow such behavior by verifying that we
only change volatile bit-field access when:
- it won't overlap with any other non-bit-field member
- we only access memory inside the bounds of the record
- avoid overlapping zero-length bit-fields.

Regarding the number of memory accesses, that should be preserved, that will
be implemented by D67399.

Differential Revision: https://reviews.llvm.org/D72932

The following people contributed to this patch:
- Diogo Sampaio
- Ties Stuij
The file was modifiedclang/lib/CodeGen/CGRecordLayoutBuilder.cpp
The file was modifiedclang/test/CodeGen/bitfield-2.c
The file was modifiedclang/test/CodeGen/aapcs-bitfield.c
The file was modifiedclang/include/clang/Basic/CodeGenOptions.def
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/CodeGen/CGExpr.cpp
The file was modifiedclang/lib/CodeGen/CGRecordLayout.h
Commit d0ccfcb040c684e91d8b5fe5111ba7f4ec7e019a by kparzysz
[GVN] Add testcase that uses masked loads and stores, NFC
The file was addedllvm/test/Transforms/GVN/masked-load-store.ll
Commit 97e77ac0ed80877cda58b1dddf98890cc7b0d167 by joker.eph
Add more explicit error message when creating a type or attribute for an unregistered dialect (NFC)

Differential Revision: https://reviews.llvm.org/D87177
The file was modifiedmlir/include/mlir/IR/AttributeSupport.h
The file was modifiedmlir/lib/Support/StorageUniquer.cpp
The file was modifiedmlir/include/mlir/IR/TypeSupport.h
The file was modifiedmlir/include/mlir/Support/StorageUniquer.h