SuccessChanges

Summary

  1. [X86] Add tests for minnum/maxnum with constant NaN (NFC) (details)
  2. [GlobalISel] Enable usage of BranchProbabilityInfo in IRTranslator. (details)
  3. Add REQUIRES: asserts to a test that uses an asserts only flag. (details)
  4. [lldb] Pass the arch as part of the triple in the ARCH_CFLAGS (details)
  5. [ARM] Add additional fmin/fmax with nan tests (NFC) (details)
  6. [DAGCombiner] Fold fmin/fmax of NaN (details)
  7. [DSE,MemorySSA] Handle atomic stores explicitly in isReadClobber. (details)
  8. [AArch64][GlobalISel] Share address mode selection code for memops (details)
Commit 91656fcb57ec6878833aba615e1142225514e13b by nikita.ppv
[X86] Add tests for minnum/maxnum with constant NaN (NFC)
The file was modifiedllvm/test/CodeGen/X86/fminnum.ll
The file was modifiedllvm/test/CodeGen/X86/fmaxnum.ll
Commit e5784ef8f6c6a7779f5dfc8f989ea37d233be388 by Amara Emerson
[GlobalISel] Enable usage of BranchProbabilityInfo in IRTranslator.

We weren't using this before, so none of the MachineFunction CFG edges had the
branch probability information added. As a result, block placement later in the
pipeline was flying blind.

This is enabled only with optimizations enabled like SelectionDAG.

Differential Revision: https://reviews.llvm.org/D86824
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetMachine.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
The file was modifiedllvm/lib/Target/X86/X86TargetMachine.cpp
The file was modifiedllvm/lib/Target/ARM/ARMTargetMachine.cpp
The file was modifiedllvm/lib/Target/Mips/MipsTargetMachine.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/phi.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetMachine.cpp
Commit a9f79707624fe20e7ac19c5063d77190baa8b281 by Amara Emerson
Add REQUIRES: asserts to a test that uses an asserts only flag.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir
Commit 2955a27abc25cd1b9d737c211c2cfe11e2a5de3e by Jonas Devlieghere
[lldb] Pass the arch as part of the triple in the ARCH_CFLAGS
The file was modifiedlldb/packages/Python/lldbsuite/test/builders/darwin.py
Commit 5a4a05c8116ebdcb434cd15796a255cf024a6bf0 by nikita.ppv
[ARM] Add additional fmin/fmax with nan tests (NFC)

Adding these to ARM which has both FMINNUM and FMINIMUM.
The file was addedllvm/test/CodeGen/ARM/fminmax-folds.ll
Commit 0a5dc7effb191eff740e0e7ae7bd8e1f6bdb3ad9 by nikita.ppv
[DAGCombiner] Fold fmin/fmax of NaN

fminnum(X, NaN) is X, fminimum(X, NaN) is NaN. This mirrors the
behavior of existing InstSimplify folds.

This is expected to improve the reduction lowerings in D87391,
which use NaN as a neutral element.

Differential Revision: https://reviews.llvm.org/D87415
The file was modifiedllvm/test/CodeGen/ARM/fminmax-folds.ll
The file was modifiedllvm/test/CodeGen/X86/fminnum.ll
The file was modifiedllvm/test/CodeGen/X86/fmaxnum.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 9969c317ff0877ed6155043422c70e1d4c028a35 by flo
[DSE,MemorySSA] Handle atomic stores explicitly in isReadClobber.

Atomic stores are modeled as MemoryDef to model the fact that they may
not be reordered, depending on the ordering constraints.

Atomic stores that are monotonic or weaker do not limit re-ordering, so
we do not have to treat them as potential read clobbers.

Note that llvm/test/Transforms/DeadStoreElimination/MSSA/atomic.ll
already contains a set of negative test cases.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D87386
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/atomic-todo.ll
The file was modifiedllvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
The file was modifiedllvm/test/Transforms/DeadStoreElimination/MSSA/atomic.ll
Commit 480e7f43a22578beaa2edc7a271e77793222a1c3 by Jessica Paquette
[AArch64][GlobalISel] Share address mode selection code for memops

We were missing support for the G_ADD_LOW + ADRP folding optimization in the
manual selection code for G_LOAD, G_STORE, and G_ZEXTLOAD.

As a result, we were missing cases like this:

```
@foo = external hidden global i32*
define void @baz(i32* %0) {
store i32* %0, i32** @foo
ret void
}
```

https://godbolt.org/z/16r7ad

This functionality already existed in the addressing mode functions for the
importer. So, this patch makes the manual selection code use
`selectAddrModeIndexed` rather than duplicating work.

This is a 0.2% geomean code size improvement for CTMark at -O3.

There is one code size increase (0.1% on lencod) which is likely because
`selectAddrModeIndexed` doesn't look through constants.

Differential Revision: https://reviews.llvm.org/D87397
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp