FailedChanges

Summary

  1. [PowerPC] Set the mayRaiseFPException for FCMPUS/FCMPUD (details)
  2. [Power10] Enable the heuristic for Power10 and switch the sched model (details)
Commit 528554c39b098e2d9a9c7ec51c77717aa07db2a2 by qshanz
[PowerPC] Set the mayRaiseFPException for FCMPUS/FCMPUD

From ISA, fcmpu will raise the Floating-Point Invalid Operation
Exception (SNaN) if either of the operands is a Signaling NaN by setting
the bit VXSNAN. But the instruction description didn't set the
mayRaiseFPException which might have impact on the scheduling or some
backend optimization.

Reviewed By: qiucf

Differential Revision: https://reviews.llvm.org/D83937
The file was addedllvm/test/CodeGen/PowerPC/nofpexcept.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
Commit 0680a3d56d8b5bcb6647a1149f0de156f72edf91 by qshanz
[Power10] Enable the heuristic for Power10 and switch the sched model
with P9 Model

Enable the pre-ra and post-ra scheduler strategy for Power10 as we want
to customize the heuristic later. And switch the scheduler model with P9
model before P10 Model is available. The NoSchedModel is modelled as
in-order cpu and the pre-ra scheduler is not bi-directional which will
have big impact on the scheduler.

Reviewed By: jji

Differential Revision: https://reviews.llvm.org/D86865
The file was modifiedllvm/lib/Target/PowerPC/PPC.td
The file was modifiedllvm/test/CodeGen/PowerPC/pcrel-call-linkage-leaf.ll
The file was modifiedllvm/test/CodeGen/PowerPC/pcrel-call-linkage-with-calls.ll
The file was modifiedllvm/test/CodeGen/PowerPC/pcrel-tail-calls.ll