SuccessChanges

Summary

  1. [TargetRegisterInfo] Add a couple of target hooks for the greedy register allocator (details)
  2. [test] Fix FullUnroll.ll (details)
  3. [AArch64] Enable implicit null check transformation (details)
  4. [RISCV] Support Shadow Call Stack (details)
  5. [MLIR][TableGen] Automatic detection and elimination of redundant methods (details)
  6. [MemorySSA] Fix an unused variable warning [NFC] (details)
  7. [PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang (details)
  8. [PowerPC] Add Set Boolean Condition Instruction Definitions and MC Tests (details)
  9. [AArch64][GlobalISel] clang-format AArch64LegalizerInfo.cpp. NFC. (details)
  10. [AArch64][GlobalISel] Make G_STORE <8 x s8> legal. (details)
  11. [lldb] Clarify docstring for SBBlock::IsInlined, NFC (details)
  12. [mlir][shape] Add `shape.cstr_require %bool` (details)
  13. [MLIR] Fix build failure due to https://reviews.llvm.org/D87059. (details)
Commit 99e865b618f31c69776273a60addbd88917a29d9 by qcolombet
[TargetRegisterInfo] Add a couple of target hooks for the greedy register allocator

Before this patch, the last chance recoloring and deferred spilling
techniques were solely controled by command line options.
This patch adds target hooks for these two techniques so that it
is easier for backend writers to override the default behavior.

The default behavior of the hooks preserves the default values of
the related command line options.

NFC
The file was modifiedllvm/include/llvm/CodeGen/TargetRegisterInfo.h
The file was modifiedllvm/lib/CodeGen/RegAllocGreedy.cpp
Commit f2f0474c93ee67421fae007528ae4be20ae384f8 by aeubanks
[test] Fix FullUnroll.ll

I believe the intention of this test added in
https://reviews.llvm.org/D71687 was to test LoopFullUnrollPass with
clang's -fno-unroll-loops, not its interaction with optnone. Loop
unrolling passes don't run under optnone/-O0.

Also added back unintentionally removed -disable-loop-unrolling from
https://reviews.llvm.org/D85578.

Reviewed By: echristo

Differential Revision: https://reviews.llvm.org/D86485
The file was modifiedllvm/test/Transforms/LoopUnroll/FullUnroll.ll
Commit b04c181ed776c344e6f5e2653a22bc6e5746834a by listmail
[AArch64] Enable implicit null check transformation

This change enables the generic implicit null transformation for the AArch64 target. As background for those unfamiliar with our implicit null check support:

    An implicit null check is the use of a signal handler to catch and redirect to a handler a null pointer. Specifically, it's replacing an explicit conditional branch with such a redirect. This is only done for very cold branches under frontend control w/appropriate metadata.
    FAULTING_OP is used to wrap the faulting instruction. It is modelled as being a conditional branch to reflect the fact it can transfer control in the CFG.
    FAULTING_OP does not need to be an analyzable branch to achieve it's purpose. (Or at least, that's the x86 model. I find this slightly questionable.)
    When lowering to MC, we convert the FAULTING_OP back into the actual instruction, record the labels, and lower the original instruction.

As can be seen in the test changes, currently the AArch64 backend does not eliminate the unconditional branch to the fallthrough block. I've tried two approaches, neither of which worked. I plan to return to this in a separate change set once I've wrapped my head around the interactions a bit better. (X86 handles this via AllowModify on analyzeBranch, but adding the obvious code causing BranchFolding to crash. I haven't yet figured out if it's a latent bug in BranchFolding, or something I'm doing wrong.)

Differential Revision: https://reviews.llvm.org/D87851
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
The file was modifiedllvm/test/CodeGen/AArch64/implicit-null-check.ll
The file was modifiedllvm/lib/CodeGen/BranchRelaxation.cpp
The file was modifiedllvm/lib/CodeGen/ImplicitNullChecks.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
Commit 1c466477ad468d8a18c43b738df7b7fc6213e9a8 by zhaoshiz
[RISCV] Support Shadow Call Stack

Currenlty assume x18 is used as pointer to shadow call stack. User shall pass
flags:

"-fsanitize=shadow-call-stack -ffixed-x18"

Runtime supported is needed to setup x18.

If SCS is desired, all parts of the program should be built with -ffixed-x18 to
maintain inter-operatability.

There's no particuluar reason that we must use x18 as SCS pointer. Any register
may be used, as long as it does not have designated purpose already, like RA or
passing call arguments.

Differential Revision: https://reviews.llvm.org/D84414
The file was modifiedclang/lib/Driver/SanitizerArgs.cpp
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
The file was addedllvm/test/CodeGen/RISCV/shadowcallstack.ll
The file was modifiedclang/test/CodeGen/shadowcallstack-attr.c
The file was modifiedclang/test/Driver/sanitizer-ld.c
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
The file was modifiedclang/lib/Driver/ToolChain.cpp
Commit 8069844577d47f503cb71644f2e58e0237d5b539 by jurahul
[MLIR][TableGen] Automatic detection and elimination of redundant methods

- Change OpClass new method addition to find and eliminate any existing methods that
  are made redundant by the newly added method, as well as detect if the newly added
  method will be redundant and return nullptr in that case.
- To facilitate that, add the notion of resolved and unresolved parameters, where resolved
  parameters have each parameter type known, so that redundancy checks on methods
  with same name but different parameter types can be done.
- Eliminate existing code to avoid adding conflicting/redundant build methods and rely
  on this new mechanism to eliminate conflicting build methods.

Fixes https://bugs.llvm.org/show_bug.cgi?id=47095

Differential Revision: https://reviews.llvm.org/D87059
The file was modifiedmlir/include/mlir/TableGen/OpClass.h
The file was modifiedmlir/test/mlir-tblgen/op-result.td
The file was modifiedmlir/test/mlir-tblgen/op-attribute.td
The file was modifiedmlir/lib/TableGen/OpClass.cpp
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
The file was modifiedmlir/tools/mlir-tblgen/OpFormatGen.cpp
Commit b4013f9c7febe70bddca16fb80a2e99623528871 by listmail
[MemorySSA] Fix an unused variable warning [NFC]
The file was modifiedllvm/include/llvm/Analysis/MemorySSA.h
Commit 2c3bc918db35913437e9302b77b11c08eb3ea6e4 by amy.kwan1
[PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang

This patch implements the vec_cntm function prototypes in altivec.h in order to
utilize the vector count mask bits instructions introduced in Power10.

Differential Revision: https://reviews.llvm.org/D82726
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td
The file was modifiedclang/test/CodeGen/builtins-ppc-p10vector.c
The file was modifiedllvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll
The file was modifiedclang/lib/Headers/altivec.h
Commit 6f3c0991bf9be48bd18a324c90e4cfcd37f82b96 by amy.kwan1
[PowerPC] Add Set Boolean Condition Instruction Definitions and MC Tests

This patch adds the instruction definitions and assembly/disassembly tests for
the set boolean condition instructions. This also includes the negative, and
reverse variants of the instruction.

Differential Revision: https://reviews.llvm.org/D86252
The file was modifiedllvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td
The file was modifiedllvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
Commit 196e2f97b714bb535a39a2daa949e523c21c0269 by Amara Emerson
[AArch64][GlobalISel] clang-format AArch64LegalizerInfo.cpp. NFC.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Commit f5898f8c2def7a1897559a7454086243b7e9ebb6 by Amara Emerson
[AArch64][GlobalISel] Make G_STORE <8 x s8> legal.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Commit 4926a5ee63017396e1c55b1505f9fd2bed858218 by Vedant Kumar
[lldb] Clarify docstring for SBBlock::IsInlined, NFC

Previously, there was a little ambiguity about whether IsInlined should
return true for an inlined lexical block, since technically the lexical
block would not represent an inlined function (it'd just be contained
within one).

Edit suggested by Jim Ingham.
The file was modifiedlldb/bindings/interface/SBBlock.i
Commit bae63742057785e03732f58d6ed1ec7bda090cc1 by silvasean
[mlir][shape] Add `shape.cstr_require %bool`

This op is a catch-all for creating witnesses from various random kinds
of constraints. In particular, I when dealing with extents directly,
which are of `index` type, one can directly use std ops for calculating
the predicates, and then use cstr_require for the final conversion to a
witness.

Differential Revision: https://reviews.llvm.org/D87871
The file was modifiedmlir/include/mlir/Dialect/Shape/IR/ShapeOps.td
The file was modifiedmlir/test/Dialect/Shape/ops.mlir
The file was modifiedmlir/lib/Dialect/Shape/IR/Shape.cpp
The file was modifiedmlir/test/Dialect/Shape/canonicalize.mlir
Commit ea237e2c8e5d082715effb9cb64158d7c6894e27 by jurahul
[MLIR] Fix build failure due to https://reviews.llvm.org/D87059.

- Remove spurious ;
- Make comparison object invokable as const.

Differential Revision: https://reviews.llvm.org/D87872
The file was modifiedmlir/include/mlir/TableGen/OpClass.h