FailedChanges

Summary

  1. [ASan][NewPM] Fix byref-args.ll under NPM (details)
  2. [Sema] Handle objc_super special lookup when checking builtin compatibility (details)
  3. DebugInfo: Tidy up initializing multi-section contributions in DWARFContext (details)
  4. [test][HWAsan] Fix kernel-inline.ll under NPM (details)
  5. [CodeGen] emit CG profile for COFF object file (details)
  6. Reapply "RegAllocFast: Record internal state based on register units" (details)
  7. RegAllocFast: Rewrite and improve (details)
  8. CodeGen: Move split block utility to MachineBasicBlock (details)
  9. [X86][AVX] Add missing non AVX512VL broadcastm test coverage (details)
  10. PR47468: Fix findPHICopyInsertPoint, so that copies aren't incorrectly inserted after an INLINEASM_BR. (details)
  11. DebugInfo: Simplify line table parsing to take all the units together, rather than CUs and TUs separately (details)
  12. Linewrap & remove some dead typedefs from previous commit (details)
  13. [InstCombine][SVE] Skip scalable type for InstCombiner::getFlippedStrictnessPredicateAndConstant. (details)
  14. [test][TSan] Fix tests under NPM (details)
  15. [X86][AVX] lowerBuildVectorAsBroadcast - improve BROADCASTM lowering on non-VLX targets (details)
  16. scudo: Add an API for disabling memory initialization per-thread. (details)
  17. First pass on MLIR python context lifetime management. (details)
  18. clangd:  Make ompletionModelCodegen.py tpy2.7 compatible (details)
  19. [gn build] (manually) port 9b6765e784b3 (details)
  20. Pre-commit test for CSEing masked loads/stores (details)
  21. [gn build] Do not sync filenames containing variable references (details)
  22. [clang-format] Recognize "hxx" as a C++ header in clang-format-diff.py (details)
  23. Temporarily Revert "[SLP] Allow reordering of vectorization trees with reused instructions." (details)
  24. [gn build] (manually) port 9b6765e784b3 more (details)
  25. [gn build] add file i forgot to add in 929d91a55616 (details)
Commit 06fe76cc4f5972b04dd4ad7b9dcb4425a73dccba by aeubanks
[ASan][NewPM] Fix byref-args.ll under NPM
The file was modifiedllvm/test/Instrumentation/AddressSanitizer/byref-args.ll
Commit a1aa330b202f97ecd243ea9ef0c7ac00a80ea653 by raul.tambre
[Sema] Handle objc_super special lookup when checking builtin compatibility

objc_super is special and needs LookupPredefedObjCSuperType() called before performing builtin type comparisons.
This fixes an error when compiling macOS headers. A test is added.

Differential Revision: https://reviews.llvm.org/D87917
The file was addedclang/test/SemaObjCXX/builtin-objcsuper.mm
The file was modifiedclang/lib/Sema/SemaDecl.cpp
Commit e0802fe0162fcab12de5f134dc0848a8e4dfbc92 by dblaikie
DebugInfo: Tidy up initializing multi-section contributions in DWARFContext
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFContext.cpp
Commit d419e34c4d7e9e0b2b3f99b77246e57a03b2459b by aeubanks
[test][HWAsan] Fix kernel-inline.ll under NPM
The file was modifiedllvm/test/Instrumentation/HWAddressSanitizer/kernel-inline.ll
Commit 91aed9bf975f1e4346cc8f4bdefc98436386ced2 by zequanwu
[CodeGen] emit CG profile for COFF object file

I forgot to add emission of CG profile for COFF object file, when adding the support (https://reviews.llvm.org/D81775)

Differential Revision: https://reviews.llvm.org/D87811
The file was modifiedllvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
The file was modifiedllvm/include/llvm/Target/TargetLoweringObjectFile.h
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was modifiedllvm/lib/Target/TargetLoweringObjectFile.cpp
The file was addedllvm/test/MC/COFF/cgprofile.ll
Commit 870fd53e4f6357946f4bad0b861c510cd107420c by Matthew.Arsenault
Reapply "RegAllocFast: Record internal state based on register units"

The regressions this caused should be fixed when
https://reviews.llvm.org/D52010 is applied.

This reverts commit a21387c65470417c58021f8d3194a4510bb64f46.
The file was modifiedllvm/test/CodeGen/X86/atomic64.ll
The file was modifiedllvm/test/CodeGen/X86/lvi-hardening-loads.ll
The file was modifiedllvm/test/CodeGen/X86/pr30813.ll
The file was modifiedllvm/test/CodeGen/X86/pr44749.ll
The file was modifiedllvm/test/CodeGen/AArch64/popcount.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-m0.ll
The file was modifiedllvm/test/CodeGen/Mips/implicit-sret.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-mask-zext-bugfix.ll
The file was modifiedllvm/test/CodeGen/X86/extend-set-cc-uses-dbg.ll
The file was modifiedllvm/test/CodeGen/X86/swift-return.ll
The file was modifiedllvm/test/CodeGen/PowerPC/addegluecrash.ll
The file was modifiedllvm/test/CodeGen/X86/crash-O0.ll
The file was modifiedllvm/test/CodeGen/X86/pr32340.ll
The file was modifiedllvm/test/CodeGen/X86/pr1489.ll
The file was modifiedllvm/test/CodeGen/X86/pr32345.ll
The file was modifiedllvm/test/CodeGen/X86/pr32284.ll
The file was modifiedllvm/test/CodeGen/X86/pr39733.ll
The file was modifiedllvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
The file was modifiedllvm/test/DebugInfo/X86/op_deref.ll
The file was modifiedllvm/test/CodeGen/X86/avx-load-store.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
The file was modifiedllvm/test/CodeGen/X86/mixed-ptr-sizes.ll
The file was modifiedllvm/test/CodeGen/Mips/atomic-min-max.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vsx.ll
The file was modifiedllvm/test/CodeGen/X86/atomic-unordered.ll
The file was modifiedllvm/test/CodeGen/X86/pr34592.ll
The file was modifiedllvm/test/CodeGen/X86/swifterror.ll
The file was modifiedllvm/test/CodeGen/X86/pr32241.ll
The file was modifiedllvm/test/CodeGen/SPARC/fp16-promote.ll
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/wwm-reserved.ll
The file was modifiedllvm/test/CodeGen/X86/pr47000.ll
The file was modifiedllvm/test/CodeGen/ARM/legalize-bitcast.ll
The file was modifiedllvm/test/CodeGen/AArch64/fast-isel-sp-adjust.ll
The file was modifiedllvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
The file was modifiedllvm/test/CodeGen/X86/fast-isel-nontemporal.ll
The file was modifiedllvm/test/CodeGen/X86/pr27591.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
The file was modifiedllvm/test/CodeGen/Mips/atomic.ll
The file was modifiedllvm/test/CodeGen/PowerPC/popcount.ll
The file was modifiedllvm/test/CodeGen/X86/atomic32.ll
The file was modifiedllvm/test/CodeGen/X86/pr30430.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll
The file was modifiedllvm/test/CodeGen/X86/pr32451.ll
Commit c8757ff3aa7dd7a25a6343f6ef74a70c7be04325 by Matthew.Arsenault
RegAllocFast: Rewrite and improve

This rewrites big parts of the fast register allocator. The basic
strategy of doing block-local allocation hasn't changed but I tweaked
several details:

Track register state on register units instead of physical
registers. This simplifies and speeds up handling of register aliases.
Process basic blocks in reverse order: Definitions are known to end
register livetimes when walking backwards (contrary when walking
forward then uses may or may not be a kill so we need heuristics).

Check register mask operands (calls) instead of conservatively
assuming everything is clobbered.  Enhance heuristics to detect
killing uses: In case of a small number of defs/uses check if they are
all in the same basic block and if so the last one is a killing use.
Enhance heuristic for copy-coalescing through hinting: We check the
first k defs of a register for COPYs rather than relying on there just
being a single definition.  When testing this on the full llvm
test-suite including SPEC externals I measured:

average 5.1% reduction in code size for X86, 4.9% reduction in code on
aarch64. (ranging between 0% and 20% depending on the test) 0.5%
faster compiletime (some analysis suggests the pass is slightly slower
than before, but we more than make up for it because later passes are
faster with the reduced instruction count)

Also adds a few testcases that were broken without this patch, in
particular bug 47278.

Patch mostly by Matthias Braun
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/callabi.ll
The file was modifiedllvm/test/DebugInfo/AArch64/frameindices.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-select.ll
The file was addedllvm/test/CodeGen/PowerPC/spill-nor0.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub_vec.ll
The file was modifiedllvm/test/CodeGen/X86/pr1489.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64_32-fastisel.ll
The file was modifiedllvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll
The file was modifiedllvm/test/CodeGen/SystemZ/swifterror.ll
The file was modifiedllvm/test/CodeGen/X86/atomic64.ll
The file was modifiedllvm/test/CodeGen/X86/pr34653.ll
The file was modifiedllvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll
The file was modifiedllvm/test/CodeGen/AArch64/combine-loads.ll
The file was modifiedllvm/test/CodeGen/Mips/atomic-min-max.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-vararg.ll
The file was modifiedllvm/test/CodeGen/X86/win64_eh.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll
The file was modifiedllvm/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll
The file was modifiedllvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll
The file was modifiedllvm/test/CodeGen/SystemZ/swift-return.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
The file was modifiedllvm/test/DebugInfo/X86/fission-ranges.ll
The file was modifiedllvm/test/CodeGen/Thumb2/high-reg-spill.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s32.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/var_arg.ll
The file was modifiedllvm/test/DebugInfo/X86/prologue-stack.ll
The file was modifiedllvm/test/CodeGen/ARM/Windows/alloca.ll
The file was modifiedllvm/test/DebugInfo/X86/subreg.ll
The file was addedllvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/wwm-reserved.ll
The file was modifiedllvm/test/CodeGen/X86/avx-load-store.ll
The file was modifiedllvm/test/CodeGen/AArch64/swifterror.ll
The file was modifiedllvm/test/CodeGen/X86/fast-isel-x86-64.ll
The file was modifiedllvm/test/CodeGen/Mips/implicit-sret.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill192.mir
The file was modifiedllvm/test/CodeGen/ARM/cmpxchg-O0.ll
The file was modifiedllvm/test/CodeGen/X86/pr47000.ll
The file was modifiedllvm/test/CodeGen/X86/x86-32-intrcc.ll
The file was modifiedllvm/test/CodeGen/X86/x86-64-intrcc.ll
The file was modifiedllvm/test/CodeGen/X86/extend-set-cc-uses-dbg.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zext_and_sext.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64_32-null.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-mask-zext-bugfix.ll
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
The file was modifiedllvm/test/CodeGen/ARM/crash-greedy-v6.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/darwin-tls-call-clobber.ll
The file was modifiedllvm/test/CodeGen/ARM/ldrd.ll
The file was modifiedllvm/test/CodeGen/X86/mixed-ptr-sizes.ll
The file was modifiedllvm/test/CodeGen/AArch64/popcount.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-m0.ll
The file was modifiedllvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll
The file was modifiedllvm/test/CodeGen/ARM/swifterror.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/brindirect.ll
The file was modifiedllvm/test/CodeGen/X86/atomic-unordered.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/test_TypeInfoforMF.ll
The file was modifiedllvm/test/CodeGen/X86/atomic6432.ll
The file was modifiedllvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll
The file was modifiedllvm/test/CodeGen/X86/pr44749.ll
The file was modifiedllvm/test/CodeGen/X86/pr30430.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm.ll
The file was modifiedllvm/test/CodeGen/PowerPC/anon_aggr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
The file was modifiedllvm/test/CodeGen/X86/crash-O0.ll
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The file was modifiedllvm/test/CodeGen/ARM/debug-info-blocks.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
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The file was modifiedllvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
The file was modifiedllvm/test/CodeGen/X86/pr32484.ll
The file was addedllvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
The file was modifiedllvm/test/DebugInfo/X86/spill-indirect-nrvo.ll
The file was modifiedllvm/test/DebugInfo/ARM/prologue_end.ll
The file was addedllvm/test/CodeGen/AMDGPU/unexpected-reg-unit-state.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/cttz.ll
The file was addedllvm/test/CodeGen/X86/bug47278-eflags-error.mir
The file was modifiedllvm/test/CodeGen/ARM/stack-guard-reassign.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll
The file was modifiedllvm/test/CodeGen/Mips/msa/ldr_str.ll
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The file was modifiedllvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
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The file was modifiedllvm/test/CodeGen/X86/stack-protector-strong-macho-win32-xor.ll
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The file was modifiedllvm/test/CodeGen/PowerPC/spill-nor0.ll
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The file was modifiedllvm/test/CodeGen/AMDGPU/spill-agpr.mir
The file was modifiedllvm/test/DebugInfo/X86/reference-argument.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_4_unaligned.ll
The file was modifiedllvm/test/CodeGen/X86/pr42452.ll
The file was modifiedllvm/test/CodeGen/Mips/atomicCmpSwapPW.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll
The file was modifiedllvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
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The file was modifiedllvm/test/CodeGen/PowerPC/stack-guard-reassign.ll
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Commit 3105d0f84bfa6b765bb88cbf090f557e588764ea by Matthew.Arsenault
CodeGen: Move split block utility to MachineBasicBlock

AMDGPU needs this in several places, so consolidate them here.
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/MachineBasicBlock.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineBasicBlock.h
The file was modifiedllvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
Commit ecba9d793e205ac857196abbd00cd67777e6f51a by llvm-dev
[X86][AVX] Add missing non AVX512VL broadcastm test coverage
The file was modifiedllvm/test/CodeGen/X86/broadcastm-lowering.ll
Commit f7a53d82c0902147909f28a9295a9d00b4b27d38 by jyknight
PR47468: Fix findPHICopyInsertPoint, so that copies aren't incorrectly inserted after an INLINEASM_BR.

findPHICopyInsertPoint special cases placement in a block with a
callbr or invoke in it. In that case, we must ensure that the copy is
placed before the INLINEASM_BR or call instruction, if the register is
defined prior to that instruction, because it may jump out of the
block.

Previously, the code placed it immediately after the last def _or
use_. This is wrong, if the use is the instruction which may jump.  We
could correctly place it immediately after the last def (ignoring
uses), but that is non-optimal for register pressure.

Instead, place the copy after the last def, or before the
call/inlineasm_br, whichever is later.

Differential Revision: https://reviews.llvm.org/D87865
The file was modifiedllvm/lib/CodeGen/PHIEliminationUtils.cpp
The file was addedllvm/test/CodeGen/X86/callbr-asm-phi-placement.ll
Commit 51a505340dfdfdfd9ab32c7267a74db3cdeefa56 by dblaikie
DebugInfo: Simplify line table parsing to take all the units together, rather than CUs and TUs separately
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFDebugLine.h
The file was modifiedllvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFContext.cpp
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
Commit 82af17cde8caa8d2d020237f644d4302fc4fa589 by dblaikie
Linewrap & remove some dead typedefs from previous commit

Cleanup for 51a505340dfdfdfd9ab32c7267a74db3cdeefa56
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFDebugLine.h
Commit 9ad6049736c58cca098b13ed128e7de0940f94a0 by huihuiz
[InstCombine][SVE] Skip scalable type for InstCombiner::getFlippedStrictnessPredicateAndConstant.

We cannot iterate on scalable vector, the number of elements is unknown at compile-time.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D87918
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
The file was addedllvm/test/Transforms/InstCombine/vscale_cmp.ll
Commit 2b1cb6d54a3298204e01a2982e3d00a1f08743a2 by aeubanks
[test][TSan] Fix tests under NPM

Under NPM, the TSan passes are split into a module and function pass. A
couple tests were testing for inserted module constructors, which is
only part of the module pass.
The file was modifiedllvm/test/Instrumentation/ThreadSanitizer/do-not-instrument-memory-access.ll
The file was modifiedllvm/test/Instrumentation/ThreadSanitizer/tsan_basic.ll
Commit 4ebd30722af5175282b99938d163ad4459aa5968 by llvm-dev
[X86][AVX] lowerBuildVectorAsBroadcast - improve BROADCASTM lowering on non-VLX targets

Broadcast to a ZMM type then extract the low subvector.
The file was modifiedllvm/test/CodeGen/X86/broadcastm-lowering.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 7bd75b630144ec639dbbf7bcb2797f48380b953b by peter
scudo: Add an API for disabling memory initialization per-thread.

Here "memory initialization" refers to zero- or pattern-init on
non-MTE hardware, or (where possible to avoid) memory tagging on MTE
hardware. With shared TSD the per-thread memory initialization state
is stored in bit 0 of the TLS slot, similar to PointerIntPair in LLVM.

Differential Revision: https://reviews.llvm.org/D87739
The file was modifiedcompiler-rt/lib/scudo/standalone/tsd_shared.h
The file was modifiedcompiler-rt/lib/scudo/standalone/include/scudo/interface.h
The file was modifiedcompiler-rt/lib/scudo/standalone/tsd_exclusive.h
The file was modifiedcompiler-rt/lib/scudo/standalone/chunk.h
The file was modifiedcompiler-rt/lib/scudo/standalone/wrappers_c.inc
The file was modifiedcompiler-rt/lib/scudo/standalone/common.h
The file was modifiedcompiler-rt/lib/scudo/standalone/tests/combined_test.cpp
The file was modifiedcompiler-rt/lib/scudo/standalone/tests/chunk_test.cpp
The file was modifiedcompiler-rt/lib/scudo/standalone/combined.h
Commit 85185b61b6371c29111611b8e3ac8d06403542c8 by stellaraccident
First pass on MLIR python context lifetime management.

* Per thread https://llvm.discourse.group/t/revisiting-ownership-and-lifetime-in-the-python-bindings/1769
* Reworks contexts so it is always possible to get back to a py::object that holds the reference count for an arbitrary MlirContext.
* Retrofits some of the base classes to automatically take a reference to the context, elimintating keep_alives.
* More needs to be done, as discussed, when moving on to the operations/blocks/regions.

Differential Revision: https://reviews.llvm.org/D87886
The file was modifiedmlir/lib/Bindings/Python/IRModules.cpp
The file was addedmlir/test/Bindings/Python/context_lifecycle.py
The file was modifiedmlir/include/mlir-c/IR.h
The file was modifiedmlir/lib/Bindings/Python/IRModules.h
The file was modifiedmlir/lib/CAPI/IR/IR.cpp
Commit 0ea2a57274225066ad81e971659222cf9ee1d12d by thakis
clangd:  Make ompletionModelCodegen.py tpy2.7 compatible

LLVM still supports Python 2.7, so unbreak bots that still run that.
In a separate commit so that this is easy to revert once we drop
support :)
The file was modifiedclang-tools-extra/clangd/quality/CompletionModelCodegen.py
Commit 442801a7b9b5460114498c48c12b8af40e495188 by thakis
[gn build] (manually) port 9b6765e784b3
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
Commit ae0ecb3c505e013659d9fa2668c55d93c1fff0b9 by kparzysz
Pre-commit test for CSEing masked loads/stores
The file was addedllvm/test/Transforms/EarlyCSE/masked-intrinsics-unequal-masks.ll
Commit 9b346f974ea606e17064969568568da30394c7a2 by thakis
[gn build] Do not sync filenames containing variable references
The file was modifiedllvm/utils/gn/build/sync_source_lists_from_cmake.py
Commit b168bbfae42e792542b4ced8729599524b9759c5 by vmiklos
[clang-format] Recognize "hxx" as a C++ header in clang-format-diff.py

And shift "proto" to the next line to avoid a too long line.

Reviewed By: MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D87931
The file was modifiedclang/tools/clang-format/clang-format-diff.py
Commit ecfd8161bf43d035eafb75c14e9cf4a6d3966946 by echristo
Temporarily Revert "[SLP] Allow reordering of vectorization trees with reused instructions."
as it's infinite looping on occasion.

This reverts commit 455ca0ebb69210046928fedffe292420a30f89ad.
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/jumbled_store_crash.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 929d91a55616d4fcf4754044b063644807b87fbe by thakis
[gn build] (manually) port 9b6765e784b3 more
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/unittests/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
Commit 7c2d83347f4ea146af1aca72fe289294aaf212be by thakis
[gn build] add file i forgot to add in 929d91a55616
The file was addedllvm/utils/gn/secondary/clang-tools-extra/clangd/quality/gen_decision_forest.gni