1. [CodeGen] Fixing inconsistent ABI mangling of vlaues in SelectionDAGBuilder (details)
  2. [Test] Test auto-update (details)
  3. [lld][ELF][test] Add additional LTO testing (details)
  4. [RISC-V] Implement RISCVInstrInfo::isCopyInstrImpl() (details)
  5. [compiler-rt] Fix atomic support functions on 32-bit architectures (details)
  6. [SyntaxTree][Synthesis] Implement `deepCopy` (details)
  7. [mlir] Shape.AssumingOp implements RegionBranchOpInterface. (details)
  8. [AArch64] Cortex-A55 scheduler model (details)
  9. [NFC][ARM] More tail predication tests. (details)
  10. [llvm-readelf/obj] - Stop printing invalid names for unnamed section symbols. (details)
  11. Do not dereference an array out of bound just to take its address (details)
  12. [ARM] Select f32 constants with vmov.f16 (details)
  13. [mlir][VectorOps] Loosen restrictions on vector.reduction types (details)
  14. Recommit "[SCEV] Look through single value PHIs." (details)
  15. [AST] Reduce the size of TemplateArgumentLocInfo. (details)
  16. Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit" (details)
  17. Fix buildbot. (details)
  18. [MLIR] Fix typo and expand gpu.host_register description. (details)
  19. [SyntaxTree][NFC] follow naming convention + remove auto on empty vector declaration (details)
Commit 53d238a961d14eae46f6f2b296ce48026c7bd0a1 by lucas.prates
[CodeGen] Fixing inconsistent ABI mangling of vlaues in SelectionDAGBuilder

SelectionDAGBuilder was inconsistently mangling values based on ABI
Calling Conventions when getting them through copyFromRegs in
SelectionDAGBuilder, causing duplicate value type convertions for
function arguments. The checking for the mangling requirement was based
on the value's originating instruction and was performed outside of, and
inspite of, the regular Calling Convention Lowering.

The issue could be observed in a scenario such as:

%arg1 = load half, half* %const, align 2
%arg2 = call fastcc half @someFunc()
call fastcc void @otherFunc(half %arg1, half %arg2)
; Here, %arg2 was incorrectly mangled twice, as the CallConv data from
; the call to @someFunc() was taken into consideration for the check
; when getting the value for processing the call to @otherFunc(...),
; after the proper convertion had taken place when lowering the return
; value of the first call.

This patch fixes the issue by disregarding the Calling Convention
information for such copyFromRegs, making sure the ABI mangling is
properly contanined in the Calling Convention Lowering.

This fixes Bugzilla #47454.

Reviewed By: efriedma

Differential Revision:
The file was addedllvm/test/CodeGen/ARM/pr47454.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Commit 98aed8aa00dcc021686972734b5356c831328721 by mkazantsev
[Test] Test auto-update
The file was modifiedllvm/test/Transforms/IndVarSimplify/eliminate-comparison.ll
Commit fa6da90aef004339e768c84d648f449348a5b13c by james.henderson
[lld][ELF][test] Add additional LTO testing

The additional testing is testing we previously had in a downstream test

Reviewed by: grimar, MaskRay

Differential Revision:
The file was addedlld/test/ELF/lto/archive-mixed.test
The file was addedlld/test/ELF/lto/undef-mixed2.test
The file was modifiedlld/test/ELF/lto/wrap-2.ll
The file was modifiedlld/test/ELF/lto/internalize-basic.ll
Commit 8cf6778d3040b33db768bb7542630d9820a72e28 by Alexander.Richardson
[RISC-V] Implement RISCVInstrInfo::isCopyInstrImpl()

This does not result in changes for any of the current tests, but it might
improve debug information in some cases.

Reviewed By: luismarques

Differential Revision:
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.h
Commit aa85c6f2a528792e2ff778a36fb6f35a01e8191c by Alexander.Richardson
[compiler-rt] Fix atomic support functions on 32-bit architectures

The code currently uses __c11_atomic_is_lock_free() to detect whether an
atomic operation is natively supported. However, this can result in a
runtime function call to determine whether the given operation is lock-free
and clang generating a call to e.g. __atomic_load_8 since the branch is
not a constant zero. Since we are implementing those runtime functions, we
must avoid those calls. This patch replaces __c11_atomic_is_lock_free()
with __atomic_always_lock_free() which always results in a compile-time
constant value. This problem was found while compiling atomic.c for MIPS32
since the -Watomic-alignment warning was being triggered and objdump showed
an undefined reference to _atomic_is_lock_free.

In addition to fixing 32-bit platforms this also enables the 16-byte case
that was disabled in r153779 (185f2edd70a34d28b305df0cd8ce519ecbca2cfd).

Reviewed By: efriedma

Differential Revision:
The file was modifiedcompiler-rt/lib/builtins/atomic.c
Commit 4a5cc389c51d267f39286a9a8c58c32f758b9d4b by ecaldas
[SyntaxTree][Synthesis] Implement `deepCopy`

Differential Revision:
The file was modifiedclang/include/clang/Tooling/Syntax/BuildTree.h
The file was modifiedclang/unittests/Tooling/Syntax/SynthesisTest.cpp
The file was modifiedclang/lib/Tooling/Syntax/Synthesis.cpp
Commit ffdd4a46a9a90d7b63b840c4b3c775074815f3ed by tpopp
[mlir] Shape.AssumingOp implements RegionBranchOpInterface.

This adds support for the interface and provides unambigious information
on the control flow as it is unconditional on any runtime values.
The code is tested through confirming that buffer-placement behaves as

Differential Revision:
The file was modifiedmlir/test/Transforms/buffer-placement.mlir
The file was modifiedmlir/include/mlir/Dialect/Shape/IR/
The file was modifiedmlir/lib/Dialect/Shape/IR/Shape.cpp
Commit 4b8ade837e36b7f0181ce86fc23f33851d0fdd35 by sjoerd.meijer
[AArch64] Cortex-A55 scheduler model

This is an initial commit adding the A55 model, but it isn't used/enabled yet.
We will follow up on this to improve the model, then flip the switch.

The optimisation guide describing Cortex-A55 micro-architecture in more detail
can be found here:

Original patch by Javed Absar.

Differential Revision:
The file was modifiedllvm/lib/Target/AArch64/
The file was addedllvm/lib/Target/AArch64/
Commit 13c73632c7cfcc2c8e70c93781d8fb9872153ede by sam.parker
[NFC][ARM] More tail predication tests.

Add mir tests for use/def of P0.
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir
Commit 095f6fbbd7b61af205d761f6951a869ec4a61722 by grimar
[llvm-readelf/obj] - Stop printing invalid names for unnamed section symbols.

We have an issue with `ELFDumper<ELFT>::getSymbolSectionName`:
1) It is used deeply for both LLVM/GNU styles and might return LLVM-style only
   values to describe symbols: "Undefined", "Processor Specific", "Absolute", etc.

2) `getSymbolSectionName` is used by `getFullSymbolName` and these special values
   might appear instead of symbol names in many places.
   This occurs for unnamed section symbols currently.

This patch extracts the LLVM specific logic to `LLVMStyle<ELFT>::printSymbolSection`,
which seems to be the only place where we want to print the special values mentioned.
It also adds a meaningful new warning that is reported when we are unable to get
a section index for a section symbol.

Differential revision:
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedllvm/test/tools/llvm-readobj/ELF/symbol-shndx.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/mips-plt.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/hash-symbols.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/dyn-symbols.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/mips-got.test
Commit 2a774411174466010c69a2460c81b8d0d4f7165f by sguelton
Do not dereference an array out of bound just to take its address

This is UB by the standard, and caught by the libstdc++ asserts

Differential Revision:
The file was modifiedflang/lib/Parser/token-sequence.cpp
Commit f4c5cadbcbb41f13cff0905449cfff4aef6a083c by
[ARM] Select f32 constants with vmov.f16

This adds lowering for f32 values using the vmov.f16, which zeroes the
top bits whilst setting the lower bits to a pattern. This range of
values does not often come up, except where a f16 constant value has
been converted to a f32.

Differential Revision:
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
The file was modifiedllvm/test/CodeGen/ARM/fp16-bitcast.ll
The file was modifiedllvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Target/ARM/
Commit 2d76274b99f2c09cdd94863d6e2e48a06f863f2a by benny.kra
[mlir][VectorOps] Loosen restrictions on vector.reduction types

LLVM can deal with any integer or float type, don't arbitrarily restrict
it to f32/f64/i32/i64.

Differential Revision:
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
The file was modifiedmlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
Commit 11dccf8d3aa5d55210f8b886fb21926c7a8353ca by flo
Recommit "[SCEV] Look through single value PHIs."

This commit was originally because it was suspected to cause a crash,
but a reproducer did not surface.

A crash that was exposed by this change was fixed in 1d8f2e52925b.

This reverts the revert commit 0581c0b0eeba03da590d1176a4580cf9b9e8d1e3.
The file was modifiedllvm/test/Analysis/ScalarEvolution/solve-quadratic-overflow.ll
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was modifiedllvm/test/Analysis/ScalarEvolution/solve-quadratic-i1.ll
The file was modifiedllvm/test/Transforms/LoopStrengthReduce/funclet.ll
Commit af29591650c43bd3bdc380c9d47b8bfd0f1664a2 by hokein.wu
[AST] Reduce the size of TemplateArgumentLocInfo.

allocate the underlying data of Template kind separately, this would reduce AST
memory usage

- TemplateArgumentLocInfo 24 => 8 bytes
- TemplateArgumentLoc  48 => 32 bytes
- DynTypeNode 56 => 40 bytes

ASTContext::.getASTAllocatedMemory changes:
  SemaDecl.cpp 255.5 MB => 247.5MB
  SemaExpr.cpp 293.5 MB => 283.5MB

Differential Revision:
The file was modifiedclang/lib/AST/TemplateBase.cpp
The file was modifiedclang/lib/Sema/SemaTemplate.cpp
The file was modifiedclang/lib/AST/TypeLoc.cpp
The file was modifiedclang/include/clang/AST/TemplateBase.h
The file was modifiedclang/lib/Sema/SemaTemplateVariadic.cpp
The file was modifiedclang/lib/AST/ASTImporter.cpp
The file was modifiedclang/lib/Sema/SemaTemplateDeduction.cpp
The file was modifiedclang/lib/Sema/TreeTransform.h
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp
The file was modifiedclang/include/clang/AST/Expr.h
The file was modifiedclang/lib/Serialization/ASTReader.cpp
Commit 17dc729bd42947b839c9717a2efa9e1e04248616 by pifon
Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit"

This reverts commit 0345d88de654259ae90494bf9b015416e2cccacb.

Google internal backend uses EntrySU, we are looking into removing
dependency on it.

Differential Revision:
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
The file was modifiedllvm/include/llvm/CodeGen/ScheduleDAG.h
The file was modifiedllvm/lib/CodeGen/MacroFusion.cpp
The file was modifiedllvm/lib/CodeGen/ScheduleDAG.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
The file was modifiedllvm/lib/CodeGen/MachineScheduler.cpp
The file was modifiedllvm/lib/CodeGen/ScheduleDAGInstrs.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
The file was modifiedllvm/lib/CodeGen/PostRASchedulerList.cpp
The file was modifiedllvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineScheduler.h
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineScheduler.h
Commit 41a8bbad5e52a94a485c5bfe3d7871784fe6d8ed by hokein.wu
Fix buildbot.

TemplateArgumentLocInfo cannot result in a constant expression anymore
after D87080.
The file was modifiedclang/include/clang/AST/TemplateBase.h
Commit 9ba3b7449d30c7a7b9be77ef3ac4016ba263b619 by csigg
[MLIR] Fix typo and expand gpu.host_register description.

See comments in

Reviewed By: herhut

Differential Revision:
The file was modifiedmlir/include/mlir/Dialect/GPU/
The file was modifiedmlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp
Commit 87f0b51d68de40e7106be89d934b5191d983e3d5 by ecaldas
[SyntaxTree][NFC] follow naming convention + remove auto on empty vector declaration

Differential Revision:
The file was modifiedclang/lib/Tooling/Syntax/BuildTree.cpp
The file was modifiedclang/lib/Tooling/Syntax/Tree.cpp
The file was modifiedclang/lib/Tooling/Syntax/Nodes.cpp