SuccessChanges

Summary

  1. clang-x86-ninja-win10 - replacing backslashes (details)
Commit bc6f110d29f33b97e734d3d9a15ec7dbc63733e3 by kuhnel
clang-x86-ninja-win10 - replacing backslashes

in buildbot.tac with forward slashes to address re-configuration
cycles in cmake
The file was modifiedbuildbot/google/docker/buildbot-windows10-vs2019/run.ps1 (diff)
The file was modifiedbuildbot/google/docker/buildbot-windows10-vs2019/VERSION (diff)
The file was modifiedbuildbot/google/terraform/main.tf (diff)

Summary

  1. Revert "Reapply Revert "RegAllocFast: Rewrite and improve"" (details)
  2. [ARM] Improve VPT predicate tracking (details)
  3. [AMDGPU] More codegen patterns for v2i16/v2f16 build_vector (details)
  4. Revert "Implement a new kind of Pass: dynamic pass pipeline" (details)
  5. [SCEV] Support unsigned predicates in isKnownPredicateViaNoOverflow (details)
  6. [MLIR][Linalg] Fix assertion in dependency analysis (details)
  7. [NFC][PowerPC]Add tests for multiply-by-constant. (details)
  8. [APFloat] multiplySignificand - always pass IEEEFloat as const reference. NFCI. (details)
  9. [PowerPC] Add support for R_PPC64_GOT_TPREL_PCREL34 used in TLS Initial Exec (details)
Commit 73a6a164b84a8195defbb8f5eeb6faecfc478ad4 by omair.javaid
Revert "Reapply Revert "RegAllocFast: Rewrite and improve""

This reverts commit 55f9f87da2c2ad791b9e62cccb1c035e037444fa.

Breaks following buildbots:
http://lab.llvm.org:8011/builders/lldb-arm-ubuntu/builds/4306
http://lab.llvm.org:8011/builders/lldb-aarch64-ubuntu/builds/9154
The file was modifiedllvm/test/CodeGen/AMDGPU/spill192.mir
The file was modifiedllvm/test/CodeGen/PowerPC/addegluecrash.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-br.ll
The file was removedllvm/test/CodeGen/X86/bug47278-eflags-error.mir
The file was modifiedllvm/test/CodeGen/X86/fast-isel-select.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-intrinsic.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll
The file was modifiedllvm/test/CodeGen/X86/2013-10-14-FastISel-incorrect-vreg.ll
The file was modifiedllvm/test/CodeGen/X86/stack-protector-strong-macho-win32-xor.ll
The file was modifiedllvm/test/CodeGen/PowerPC/anon_aggr.ll
The file was modifiedllvm/test/DebugInfo/X86/op_deref.ll
The file was modifiedllvm/test/CodeGen/ARM/ldrd.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zext_and_sext.ll
The file was modifiedllvm/test/CodeGen/Mips/atomic64.ll
The file was modifiedllvm/test/CodeGen/AArch64/unwind-preserved.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll
The file was modifiedllvm/test/CodeGen/PowerPC/spill-nor0.ll
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll
The file was modifiedllvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll
The file was modifiedllvm/test/CodeGen/X86/pr39733.ll
The file was modifiedllvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-vararg.ll
The file was modifiedllvm/test/CodeGen/Mips/atomicCmpSwapPW.ll
The file was modifiedllvm/test/CodeGen/AArch64/swift-return.ll
The file was modifiedllvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
The file was modifiedllvm/test/CodeGen/X86/atomic-unordered.ll
The file was modifiedllvm/test/CodeGen/AArch64/combine-loads.ll
The file was modifiedllvm/test/CodeGen/Mips/micromips-eva.mir
The file was modifiedllvm/test/CodeGen/X86/fast-isel-nontemporal.ll
The file was modifiedllvm/test/DebugInfo/X86/sret.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-mask-zext-bugfix.ll
The file was modifiedllvm/test/CodeGen/ARM/crash-greedy-v6.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vector-spill.ll
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The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address_pic.ll
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The file was modifiedllvm/test/CodeGen/X86/pr1489.ll
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The file was modifiedllvm/test/CodeGen/X86/swift-return.ll
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The file was removedllvm/test/CodeGen/AMDGPU/unexpected-reg-unit-state.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll
The file was removedllvm/test/CodeGen/PowerPC/spill-nor0.mir
The file was modifiedllvm/test/CodeGen/Thumb2/high-reg-spill.mir
The file was modifiedllvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll
The file was modifiedllvm/test/CodeGen/X86/fast-isel-select-sse.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fp64-to-int16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wwm-reserved.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctlz.ll
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The file was modifiedllvm/test/CodeGen/X86/fast-isel-cmp-branch.ll
The file was modifiedllvm/test/CodeGen/X86/pr47000.ll
The file was modifiedllvm/test/DebugInfo/X86/parameters.ll
The file was modifiedllvm/test/CodeGen/X86/atomic6432.ll
The file was modifiedllvm/test/CodeGen/ARM/debug-info-blocks.ll
The file was modifiedllvm/test/CodeGen/X86/pr32284.ll
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The file was modifiedllvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
The file was modifiedllvm/test/CodeGen/X86/mixed-ptr-sizes.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vsx.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-overflow-toc.py
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
The file was modifiedllvm/test/DebugInfo/X86/reference-argument.ll
The file was modifiedllvm/test/CodeGen/X86/x86-64-intrcc.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll
The file was modifiedllvm/test/CodeGen/PowerPC/popcount.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/cttz.ll
The file was modifiedllvm/test/CodeGen/X86/pr27591.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll
The file was modifiedllvm/test/CodeGen/AArch64/br-cond-not-merge.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
The file was modifiedllvm/test/CodeGen/ARM/Windows/alloca.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/var_arg.ll
The file was removedllvm/test/CodeGen/X86/bug47278.mir
The file was modifiedllvm/test/CodeGen/X86/pr32345.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll
The file was modifiedllvm/test/CodeGen/PowerPC/stack-guard-reassign.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/dyn_stackalloc.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_split_because_of_memsize_or_align.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/reserve-vgpr-for-sgpr-spill.ll
The file was modifiedllvm/test/CodeGen/PowerPC/elf-common.ll
The file was modifiedllvm/test/CodeGen/SystemZ/swifterror.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
The file was modifiedllvm/test/CodeGen/ARM/thumb-big-stack.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
The file was modifiedllvm/test/CodeGen/X86/pr11415.ll
The file was modifiedllvm/test/CodeGen/X86/pr34653.ll
The file was modifiedllvm/test/CodeGen/AArch64/fast-isel-cmpxchg.ll
The file was modifiedllvm/test/CodeGen/AArch64/popcount.ll
The file was modifiedllvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/call.ll
The file was modifiedllvm/test/CodeGen/X86/pr32484.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-agpr.mir
The file was modifiedllvm/test/CodeGen/ARM/cmpxchg-O0-be.ll
The file was modifiedllvm/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll
The file was modifiedllvm/test/DebugInfo/X86/fission-ranges.ll
The file was modifiedllvm/test/CodeGen/ARM/stack-guard-reassign.ll
The file was modifiedllvm/test/CodeGen/X86/atomic64.ll
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The file was modifiedllvm/test/CodeGen/AArch64/arm64_32-null.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/brindirect.ll
The file was modifiedllvm/test/CodeGen/X86/win64_eh.ll
The file was modifiedllvm/test/CodeGen/SystemZ/swift-return.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/test_TypeInfoforMF.ll
The file was modifiedllvm/test/CodeGen/X86/phys-reg-local-regalloc.ll
The file was modifiedllvm/test/CodeGen/Mips/msa/ldr_str.ll
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
The file was modifiedllvm/test/CodeGen/X86/atomic-monotonic.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64_32-fastisel.ll
The file was modifiedllvm/test/DebugInfo/AArch64/prologue_end.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/darwin-tls-call-clobber.ll
The file was modifiedllvm/test/CodeGen/Mips/atomic-min-max.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s64.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_4_unaligned.ll
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The file was modifiedllvm/test/DebugInfo/X86/dbg-declare-arg.ll
The file was modifiedllvm/test/CodeGen/ARM/pr47454.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll
The file was modifiedllvm/test/DebugInfo/Mips/delay-slot.ll
The file was modifiedlldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
The file was modifiedllvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
The file was modifiedllvm/test/CodeGen/X86/avx-load-store.ll
The file was modifiedllvm/test/CodeGen/X86/pr32241.ll
The file was modifiedllvm/test/DebugInfo/Mips/prologue_end.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_split_because_of_memsize_or_align.ll
The file was modifiedllvm/test/CodeGen/X86/pr30430.ll
The file was removedllvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir
The file was modifiedllvm/test/DebugInfo/X86/pieces-1.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-m0.ll
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The file was removedllvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir
The file was modifiedllvm/test/CodeGen/X86/pr30813.ll
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The file was modifiedllvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll
The file was modifiedllvm/test/DebugInfo/X86/subreg.ll
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
The file was modifiedllvm/test/CodeGen/Mips/implicit-sret.ll
The file was modifiedllvm/test/DebugInfo/ARM/prologue_end.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vsx-args.ll
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The file was modifiedllvm/test/CodeGen/ARM/fast-isel-call.ll
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The file was modifiedllvm/test/CodeGen/X86/pr34592.ll
The file was modifiedllvm/test/CodeGen/X86/fast-isel-x86-64.ll
Commit b4fa884a73c5c883723738f67ad1810a6d48cc2d by sam.parker
[ARM] Improve VPT predicate tracking

The VPTBlock has been modified to track the 'global' state of the
VPR, as well as the state for each block. Each object now just holds
a list of instructions that makeup the block, while static structures
hold the predicate information. This enables global access for
querying how both a VPT block and individual instructions are
predicated. These changes now allow us, again, to handle more
complicated cases where multiple instructions build a predicate
and/or where the same predicate in used in multiple blocks.

It doesn't, however, get us back to before the tracking was 'fixed'
as some extra logic will be required to properly handle VPT
instructions. Currently a VPT could be effectively predicated because
of it's inputs, but the existing logic will not detect that and so
will refuse to perform the transformation. This can be seen in
remat-vctp.ll test where we still don't perform the transform.

Differential Revision: https://reviews.llvm.org/D87681
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/tp-multiple-vpst.ll
Commit 892ef2e3c0b60656a95d0d9e9f458b73238b21b7 by jay.foad
[AMDGPU] More codegen patterns for v2i16/v2f16 build_vector

It's simpler to do this at codegen time than to do ad-hoc constant
folding of machine instructions in SIFoldOperands.

Differential Revision: https://reviews.llvm.org/D88028
The file was modifiedllvm/lib/Target/AMDGPU/SIFoldOperands.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
Commit 0356a413a443864409f966b069656814f10e7710 by benny.kra
Revert "Implement a new kind of Pass: dynamic pass pipeline"

This reverts commit 385c3f43fceba227be2e4dce84a59075733541c1.

Test  mlir/test/Pass:dynamic-pipeline-fail-on-parent.mlir.test fails
when run with ASAN:

ERROR: AddressSanitizer: stack-use-after-scope on address ...

Reviewed By: bkramer, pifon2a

Differential Revision: https://reviews.llvm.org/D88079
The file was modifiedmlir/tools/mlir-opt/mlir-opt.cpp
The file was modifiedmlir/include/mlir/Pass/PassManager.h
The file was removedmlir/test/lib/Transforms/TestDynamicPipeline.cpp
The file was modifiedmlir/include/mlir/Pass/Pass.h
The file was modifiedmlir/lib/Pass/Pass.cpp
The file was removedmlir/test/Pass/dynamic-pipeline.mlir
The file was removedmlir/test/Pass/dynamic-pipeline-fail-on-parent.mlir
The file was removedmlir/test/Pass/dynamic-pipeline-nested.mlir
The file was modifiedmlir/test/lib/Transforms/CMakeLists.txt
Commit 16fde88dbd797b01f3c236062fbec50fe5bbf81d by mkazantsev
[SCEV] Support unsigned predicates in isKnownPredicateViaNoOverflow

SCEV should be able to prove facts like `x <u x+1<nuw>`.

Differential Revision: https://reviews.llvm.org/D88015
Reviewed By: lebedev.ri
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was modifiedllvm/unittests/Analysis/ScalarEvolutionTest.cpp
Commit 0841f7172b74e1cbe2ce9839e5f4e1f0c2836bef by frgossen
[MLIR][Linalg] Fix assertion in dependency analysis

The assertion falsely expected ranked memrefs only.  Now both, ranked and
unranked memrefs are allowed.

Differential Revision: https://reviews.llvm.org/D88080
The file was modifiedmlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp
Commit c7ff6e0fe1cd37a162af5f30d8cb070eb4cc038d by esme.yi
[NFC][PowerPC]Add tests for multiply-by-constant.
The file was modifiedllvm/test/CodeGen/PowerPC/mulli.ll
Commit f835779160ec30340676918915526615a07e826e by llvm-dev
[APFloat] multiplySignificand - always pass IEEEFloat as const reference. NFCI.

We do this in all other cases.
The file was modifiedllvm/include/llvm/ADT/APFloat.h
The file was modifiedllvm/lib/Support/APFloat.cpp
Commit c0071862bb426689acef09491b01b1edca9d747e by stefanp
[PowerPC] Add support for R_PPC64_GOT_TPREL_PCREL34 used in TLS Initial Exec

Add Thread Local Storage Initial Exec support to LLD.

This patch adds the computation for the relocations as well as the relaxation from Initial Exec to Local Exec.

Initial Exec:
```
pld r9, x@got@tprel@pcrel
add r9, r9, x@tls@pcrel
```
or
```
pld r9, x@got@tprel@pcrel
lbzx r10, r9, x@tls@pcrel
```
Note that @tls@pcrel is actually encoded as R_PPC64_TLS with a one byte displacement.

For the above examples relaxing Intitial Exec to Local Exec:
```
paddi r9, r9, x@tprel
nop
```
or
```
paddi r9, r13, x@tprel
lbz r10, 0(r9)
```

Reviewed By: nemanjai, MaskRay, #powerpc

Differential Revision: https://reviews.llvm.org/D86893
The file was modifiedlld/ELF/Arch/PPC64.cpp
The file was addedlld/test/ELF/ppc64-tls-pcrel-ie.s

Summary

  1. clang-x86-ninja-win10 - replacing backslashes (details)
Commit bc6f110d29f33b97e734d3d9a15ec7dbc63733e3 by kuhnel
clang-x86-ninja-win10 - replacing backslashes

in buildbot.tac with forward slashes to address re-configuration
cycles in cmake
The file was modifiedbuildbot/google/docker/buildbot-windows10-vs2019/run.ps1
The file was modifiedbuildbot/google/docker/buildbot-windows10-vs2019/VERSION
The file was modifiedbuildbot/google/terraform/main.tf