FailedChanges

Summary

  1. Added x86_64-fedora-clang builder and fedora-llvm-x86_64 slave (details)
Commit d5933da06ce30de8cfec8ea57f8ecce0d094cb9c by kkleine
Added x86_64-fedora-clang builder and fedora-llvm-x86_64 slave

I'm evaluating how to run a buildbot slave/worker in a Red Hat internal OpenShift cluster.

Differential Revision: https://reviews.llvm.org/D88007
The file was modifiedbuildbot/osuosl/master/config/slaves.py (diff)
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)

Summary

  1. [PowerPC] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins (details)
  2. Revert "[RISCV][ASAN] implementation of ThreadSelf  for riscv64" (details)
  3. [NFC] Reformat preprocessor directives (details)
  4. [RISCV][ASAN] implementation of ThreadSelf  for riscv64 (details)
  5. [mlir][Linalg] Add pattern to fold linalg.tensor_reshape that add unit extent dims. (details)
  6. [AMDGPU] Fix merging m0 inits (details)
  7. [SVE] Fix InstCombinerImpl::PromoteCastOfAllocation for scalable vectors (details)
  8. Revert "[libc++] Implement LWG1203" (details)
  9. [SVE] Make EVT::getScalarSizeInBits and others consistent with Type::getScalarSizeInBits (details)
  10. [analyzer][StdLibraryFunctionsChecker] Fix getline/getdelim signatures (details)
  11. [analyzer][StdLibraryFunctionsChecker] Separate the signature from the summaries (details)
Commit d7eb917a7cb793f49e16841fc24826b988dd5c8f by albionapc
[PowerPC] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins

This patch implements 128-bit Binary Vector Mod and Sign Extend builtins for PowerPC10.

Differential: https://reviews.llvm.org/D87394#inline-815858
The file was modifiedclang/test/CodeGen/builtins-ppc-p9vector.c
The file was modifiedllvm/test/CodeGen/PowerPC/p10-vector-modulo.ll
The file was addedllvm/test/CodeGen/PowerPC/p10-vector-sign-extend.ll
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrAltivec.td
The file was addedllvm/test/CodeGen/PowerPC/p9-vector-sign-extend.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrPrefix.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was modifiedclang/test/CodeGen/builtins-ppc-p10vector.c
The file was modifiedclang/lib/Headers/altivec.h
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
Commit 1fbb5969424493344f1159d53bda5a640e3b27ae by Vitaly Buka
Revert "[RISCV][ASAN] implementation of ThreadSelf  for riscv64"

Merged two unrelated commits

This reverts commit 00f6ebef6e347e0d24a8f940fe43656719e88cb8.
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
Commit d721a2bc335ad01ff6b3838bc4759cfc35b6c8fa by Vitaly Buka
[NFC] Reformat preprocessor directives
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
Commit 809a42e3d53518b824aad28882f9f9397f25b5b3 by Vitaly Buka
[RISCV][ASAN] implementation of ThreadSelf  for riscv64

[6/11] patch series to port ASAN for riscv64

Depends On D87574

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D87575
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
Commit b62f9f4407a5ed6e5722e177e906efcebebce9eb by ravishankarm
[mlir][Linalg] Add pattern to fold linalg.tensor_reshape that add unit extent dims.

A sequence of two reshapes such that one of them is just adding unit
extent dims can be folded to a single reshape.

Differential Revision: https://reviews.llvm.org/D88057
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir
Commit 8d7fd73c3a8ce069cfe48dfcf949b4a59c05c673 by Piotr Sobczak
[AMDGPU] Fix merging m0 inits

Fix incorrect merges of m0 inits in loops.

It was assumed that if a clobbering instruction appears in
the same block as an init and the clobbering instruction
does not dominate the init then it does not interfere with
init.

This does not work in the presence of loops, where in this
scenario, the clobbering instruction does interfere with
the init in another iteration.

To fix this, do not check for block equality and defer the
decision to the predecessor check.

Differential Revision: https://reviews.llvm.org/D87882
The file was modifiedllvm/test/CodeGen/AMDGPU/merge-m0.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
Commit 59c4d5aad060927fa95b917c11aad4e310849a4b by david.sherwood
[SVE] Fix InstCombinerImpl::PromoteCastOfAllocation for scalable vectors

In this patch I've fixed some warnings that arose from the implicit
cast of TypeSize -> uint64_t. I tried writing a variety of different
cases to show how this optimisation might work for scalable vectors
and found:

1. The optimisation does not work for cases where the cast type
is scalable and the allocated type is not. This because we need to
know how many times the cast type fits into the allocated type.
2. If we pass all the various checks for the case when the allocated
type is scalable and the cast type is not, then when creating the
new alloca we have to take vscale into account. This leads to
sub-optimal IR that is worse than the original IR.
3. For the remaining case when both the alloca and cast types are
scalable it is hard to find examples where the optimisation would
kick in, except for simple bitcasts, because we typically fail the
ABI alignment checks.

For now I've changed the code to bail out if only one of the alloca
and cast types is scalable. This means we continue to support the
existing cases where both types are fixed, and also the specific case
when both types are scalable with the same size and alignment, for
example a simple bitcast of an alloca to another type.

I've added tests that show we don't attempt to promote the alloca,
except for simple bitcasts:

  Transforms/InstCombine/AArch64/sve-cast-of-alloc.ll

Differential revision: https://reviews.llvm.org/D87378
The file was addedllvm/test/Transforms/InstCombine/AArch64/sve-cast-of-alloc.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
Commit e46c1def523323eedfad1174fd2fabbece8f40cc by Raphael Isemann
Revert "[libc++] Implement LWG1203"

This reverts commit fdc41e11f9687a50c97e2a59663bf2d541ff5489. It causes the
libcxx/modules/stds_include.sh.cpp test to fail with:
libcxx/include/ostream:1039:45: error: no template named 'enable_if_t'; did you mean 'enable_if'?
template <class _Stream, class _Tp, class = enable_if_t<

Still investigating what's causing this and reverting in the meantime to get
the bots green again.
The file was modifiedlibcxx/include/istream
The file was modifiedlibcxx/test/std/input.output/iostream.format/input.streams/istream.rvalue/rvalue.pass.cpp
The file was removedlibcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/rvalue.pass.cpp
The file was addedlibcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/CharT_pointer.pass.cpp
The file was removedlibcxx/test/std/input.output/iostream.format/output.streams/ostream.rvalue/not_ostreamable.verify.cpp
The file was modifiedlibcxx/www/cxx2a_status.html
The file was modifiedlibcxx/include/ostream
The file was removedlibcxx/test/std/input.output/iostream.format/input.streams/istream.rvalue/not_istreamable.verify.cpp
Commit e077367a28102128483f4b2555d2ad31e21b1965 by david.sherwood
[SVE] Make EVT::getScalarSizeInBits and others consistent with Type::getScalarSizeInBits

An existing function Type::getScalarSizeInBits returns a uint64_t
instead of a TypeSize class because the caller is requesting a
scalar size, which cannot be scalable. This patch makes other
similar functions requesting a scalar size consistent with that,
thereby eliminating more than 1000 implicit TypeSize -> uint64_t
casts.

Differential revision: https://reviews.llvm.org/D87889
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/include/llvm/Support/MachineValueType.h
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/ValueTypes.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAGNodes.h
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit d63a945a13048b66f06e222d8b0810d7db9592f6 by gabor.marton
[analyzer][StdLibraryFunctionsChecker] Fix getline/getdelim signatures

It is no longer needed to add summaries of 'getline' for different
possible underlying types of ssize_t. We can just simply lookup the
type.

Differential Revision: https://reviews.llvm.org/D88092
The file was modifiedclang/test/Analysis/std-c-library-functions.c
The file was modifiedclang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
Commit 11d2e63ab0060c656398afd8ea26760031a9fb96 by gabor.marton
[analyzer][StdLibraryFunctionsChecker] Separate the signature from the summaries

The signature should not be part of the summaries as many FIXME comments
suggests. By separating the signature, we open up the way to a generic
matching implementation which could be used later under the hoods of
CallDescriptionMap.

Differential Revision: https://reviews.llvm.org/D88100
The file was modifiedclang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp

Summary

  1. Added x86_64-fedora-clang builder and fedora-llvm-x86_64 slave (details)
Commit d5933da06ce30de8cfec8ea57f8ecce0d094cb9c by kkleine
Added x86_64-fedora-clang builder and fedora-llvm-x86_64 slave

I'm evaluating how to run a buildbot slave/worker in a Red Hat internal OpenShift cluster.

Differential Revision: https://reviews.llvm.org/D88007
The file was modifiedbuildbot/osuosl/master/config/builders.py
The file was modifiedbuildbot/osuosl/master/config/slaves.py